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// File : ../RTL/serialInterfaceEngine/processTxByte.v
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// Generated : 10/06/06 19:35:29
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// From : ../RTL/serialInterfaceEngine/processTxByte.asf
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// By : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// processTxByte
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//// processTxByte
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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| Line 40... |
Line 45... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
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module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);
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input clk;
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input [1:0]JBit;
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input [1:0]JBit;
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input [1:0]KBit;
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input [1:0]KBit;
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input processTxByteWEn;
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input rst;
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input [7:0]TxByteCtrlIn;
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input [7:0]TxByteCtrlIn;
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input TxByteFullSpeedRateIn;
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input TxByteFullSpeedRateIn;
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input [7:0]TxByteIn;
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input [7:0]TxByteIn;
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input USBWireGnt;
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input USBWireGnt;
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input USBWireRdy;
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input USBWireRdy;
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output processTxByteRdy;
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input clk;
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input processTxByteWEn;
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input rst;
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output USBWireCtrl;
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output USBWireCtrl;
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output [1:0]USBWireData;
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output [1:0]USBWireData;
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output USBWireFullSpeedRate;
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output USBWireFullSpeedRate;
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output USBWireReq;
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output USBWireReq;
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output USBWireWEn;
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output USBWireWEn;
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output processTxByteRdy;
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wire clk;
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wire [1:0]JBit;
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wire [1:0]JBit;
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wire [1:0]KBit;
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wire [1:0]KBit;
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reg processTxByteRdy, next_processTxByteRdy;
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wire processTxByteWEn;
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wire rst;
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wire [7:0]TxByteCtrlIn;
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wire [7:0]TxByteCtrlIn;
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wire TxByteFullSpeedRateIn;
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wire TxByteFullSpeedRateIn;
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wire [7:0]TxByteIn;
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wire [7:0]TxByteIn;
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reg USBWireCtrl, next_USBWireCtrl;
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reg USBWireCtrl, next_USBWireCtrl;
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reg [1:0]USBWireData, next_USBWireData;
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reg [1:0]USBWireData, next_USBWireData;
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reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
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reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
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wire USBWireGnt;
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wire USBWireGnt;
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wire USBWireRdy;
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wire USBWireRdy;
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reg USBWireReq, next_USBWireReq;
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reg USBWireReq, next_USBWireReq;
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reg USBWireWEn, next_USBWireWEn;
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reg USBWireWEn, next_USBWireWEn;
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wire clk;
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reg processTxByteRdy, next_processTxByteRdy;
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wire processTxByteWEn;
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wire rst;
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// diagram signals declarations
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// diagram signals declarations
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reg [3:0]i, next_i;
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reg [7:0]TxByte, next_TxByte;
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reg [7:0]TxByteCtrl, next_TxByteCtrl;
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reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
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reg [1:0]TXLineState, next_TXLineState;
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reg [1:0]TXLineState, next_TXLineState;
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reg [3:0]TXOneCount, next_TXOneCount;
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reg [3:0]TXOneCount, next_TXOneCount;
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reg [7:0]TxByteCtrl, next_TxByteCtrl;
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reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
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reg [7:0]TxByte, next_TxByte;
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reg [3:0]i, next_i;
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// BINARY ENCODED state machine: prcTxB
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// BINARY ENCODED state machine: prcTxB
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// State codes definitions:
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// State codes definitions:
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`define START_PTBY 5'b00000
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`define START_PTBY 5'b00000
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`define PTBY_WAIT_EN 5'b00001
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`define PTBY_WAIT_EN 5'b00001
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| Line 119... |
Line 124... |
`define STOP_W_RDY1 5'b11001
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`define STOP_W_RDY1 5'b11001
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`define STOP_W_RDY2 5'b11010
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`define STOP_W_RDY2 5'b11010
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`define STOP_W_RDY3 5'b11011
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`define STOP_W_RDY3 5'b11011
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`define STOP_W_RDY4 5'b11100
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`define STOP_W_RDY4 5'b11100
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reg [4:0]CurrState_prcTxB, NextState_prcTxB;
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reg [4:0] CurrState_prcTxB;
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reg [4:0] NextState_prcTxB;
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//--------------------------------------------------------------------
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// Machine: prcTxB
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// Machine: prcTxB
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//--------------------------------------------------------------------
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or TxByteFullSpeedRate or CurrState_prcTxB)
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// Next State Logic (combinatorial)
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begin
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//----------------------------------
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always @ (TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteFullSpeedRate or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or CurrState_prcTxB)
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begin : prcTxB_NextState
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NextState_prcTxB <= CurrState_prcTxB;
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NextState_prcTxB <= CurrState_prcTxB;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_processTxByteRdy <= processTxByteRdy;
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next_processTxByteRdy <= processTxByteRdy;
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next_USBWireData <= USBWireData;
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next_USBWireData <= USBWireData;
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next_USBWireCtrl <= USBWireCtrl;
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next_USBWireCtrl <= USBWireCtrl;
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| Line 141... |
Line 150... |
next_TxByteCtrl <= TxByteCtrl;
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next_TxByteCtrl <= TxByteCtrl;
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next_TXLineState <= TXLineState;
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next_TXLineState <= TXLineState;
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next_TXOneCount <= TXOneCount;
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next_TXOneCount <= TXOneCount;
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next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
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next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
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next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
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next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
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case (CurrState_prcTxB) // synopsys parallel_case full_case
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case (CurrState_prcTxB)
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`START_PTBY:
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`START_PTBY:
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begin
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begin
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next_processTxByteRdy <= 1'b0;
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next_processTxByteRdy <= 1'b0;
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next_USBWireData <= 2'b00;
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next_USBWireData <= 2'b00;
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next_USBWireCtrl <= `TRI_STATE;
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next_USBWireCtrl <= `TRI_STATE;
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| Line 185... |
Line 194... |
next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
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next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
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next_i <= 4'h0;
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next_i <= 4'h0;
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end
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end
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end
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end
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`PTBY_WAIT_GNT:
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`PTBY_WAIT_GNT:
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begin
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if (USBWireGnt == 1'b1)
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if (USBWireGnt == 1'b1)
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begin
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NextState_prcTxB <= `WAIT_RDY_WIRE;
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NextState_prcTxB <= `WAIT_RDY_WIRE;
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end
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end
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`WAIT_RDY_WIRE:
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`WAIT_RDY_WIRE:
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begin
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if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate == 1'b0))
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if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate == 1'b0))
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begin
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NextState_prcTxB <= `LS_START_SND_IDLE1;
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NextState_prcTxB <= `LS_START_SND_IDLE1;
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end
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else if (USBWireRdy == 1'b1)
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else if (USBWireRdy == 1'b1)
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begin
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begin
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NextState_prcTxB <= `WAIT_RDY_PKT;
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NextState_prcTxB <= `WAIT_RDY_PKT;
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//actively drive the first J bit
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//actively drive the first J bit
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next_USBWireData <= JBit;
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next_USBWireData <= JBit;
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next_USBWireCtrl <= `DRIVE;
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next_USBWireCtrl <= `DRIVE;
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next_USBWireWEn <= 1'b1;
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next_USBWireWEn <= 1'b1;
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end
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end
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end
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`WAIT_RDY_PKT:
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`WAIT_RDY_PKT:
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begin
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begin
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next_USBWireWEn <= 1'b0;
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next_USBWireWEn <= 1'b0;
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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next_i <= 4'h0;
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next_i <= 4'h0;
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| Line 232... |
Line 233... |
next_TXLineState <= JBit;
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next_TXLineState <= JBit;
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end
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end
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NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
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NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
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end
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end
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`SEND_BYTE_WAIT_RDY:
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`SEND_BYTE_WAIT_RDY:
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begin
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if (USBWireRdy == 1'b1)
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if (USBWireRdy == 1'b1)
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begin
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begin
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NextState_prcTxB <= `SEND_BYTE_CHK;
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NextState_prcTxB <= `SEND_BYTE_CHK;
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next_USBWireWEn <= 1'b1;
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next_USBWireWEn <= 1'b1;
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next_USBWireData <= TXLineState;
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next_USBWireData <= TXLineState;
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next_USBWireCtrl <= `DRIVE;
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next_USBWireCtrl <= `DRIVE;
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end
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end
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end
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`SEND_BYTE_CHK:
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`SEND_BYTE_CHK:
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begin
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begin
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next_USBWireWEn <= 1'b0;
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next_USBWireWEn <= 1'b0;
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if (TXOneCount == `MAX_CONSEC_SAME_BITS)
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if (TXOneCount == `MAX_CONSEC_SAME_BITS)
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begin
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NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
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NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
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end
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else if (i != 4'h8)
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else if (i != 4'h8)
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begin
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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end
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else
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else
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begin
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NextState_prcTxB <= `STOP_CHK;
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NextState_prcTxB <= `STOP_CHK;
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end
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end
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end
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`SEND_BYTE_BIT_STUFF:
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`SEND_BYTE_BIT_STUFF:
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begin
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begin
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next_TXOneCount <= 4'h0;
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next_TXOneCount <= 4'h0;
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//reset 'TXOneCount'
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//reset 'TXOneCount'
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if (TXLineState == JBit)
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if (TXLineState == JBit)
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| Line 269... |
Line 262... |
else
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else
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next_TXLineState <= JBit;
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next_TXLineState <= JBit;
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NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
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NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
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end
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end
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`SEND_BYTE_WAIT_RDY2:
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`SEND_BYTE_WAIT_RDY2:
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begin
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if (USBWireRdy == 1'b1)
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if (USBWireRdy == 1'b1)
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begin
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begin
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NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
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NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
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next_USBWireWEn <= 1'b1;
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next_USBWireWEn <= 1'b1;
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next_USBWireData <= TXLineState;
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next_USBWireData <= TXLineState;
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next_USBWireCtrl <= `DRIVE;
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next_USBWireCtrl <= `DRIVE;
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end
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end
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end
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`SEND_BYTE_CHK_FIN:
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`SEND_BYTE_CHK_FIN:
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begin
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begin
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next_USBWireWEn <= 1'b0;
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next_USBWireWEn <= 1'b0;
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if (i == 4'h8)
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if (i == 4'h8)
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begin
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NextState_prcTxB <= `STOP_CHK;
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NextState_prcTxB <= `STOP_CHK;
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end
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else
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else
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begin
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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end
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end
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end
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`STOP_SND_SE0_2:
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`STOP_SND_SE0_2:
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begin
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begin
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next_USBWireWEn <= 1'b0;
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next_USBWireWEn <= 1'b0;
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NextState_prcTxB <= `STOP_W_RDY2;
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NextState_prcTxB <= `STOP_W_RDY2;
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end
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end
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`STOP_SND_SE0_1:
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`STOP_SND_SE0_1:
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begin
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NextState_prcTxB <= `STOP_W_RDY1;
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NextState_prcTxB <= `STOP_W_RDY1;
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end
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`STOP_CHK:
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`STOP_CHK:
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begin
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if (TxByteCtrl == `DATA_STOP)
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if (TxByteCtrl == `DATA_STOP)
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begin
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NextState_prcTxB <= `STOP_SND_SE0_1;
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NextState_prcTxB <= `STOP_SND_SE0_1;
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end
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else
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else
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begin
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NextState_prcTxB <= `PTBY_WAIT_EN;
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NextState_prcTxB <= `PTBY_WAIT_EN;
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end
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end
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`STOP_SND_J:
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`STOP_SND_J:
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begin
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begin
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next_USBWireWEn <= 1'b0;
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next_USBWireWEn <= 1'b0;
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NextState_prcTxB <= `STOP_W_RDY3;
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NextState_prcTxB <= `STOP_W_RDY3;
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end
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end
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| Line 328... |
Line 307... |
next_USBWireReq <= 1'b0;
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next_USBWireReq <= 1'b0;
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//release the wire
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//release the wire
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NextState_prcTxB <= `PTBY_WAIT_EN;
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NextState_prcTxB <= `PTBY_WAIT_EN;
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end
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end
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`STOP_W_RDY1:
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`STOP_W_RDY1:
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begin
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if (USBWireRdy == 1'b1)
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if (USBWireRdy == 1'b1)
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begin
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begin
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NextState_prcTxB <= `STOP_SND_SE0_2;
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NextState_prcTxB <= `STOP_SND_SE0_2;
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next_USBWireWEn <= 1'b1;
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next_USBWireWEn <= 1'b1;
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next_USBWireData <= `SE0;
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next_USBWireData <= `SE0;
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next_USBWireCtrl <= `DRIVE;
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next_USBWireCtrl <= `DRIVE;
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end
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end
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end
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`STOP_W_RDY2:
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`STOP_W_RDY2:
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begin
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if (USBWireRdy == 1'b1)
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if (USBWireRdy == 1'b1)
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begin
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begin
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NextState_prcTxB <= `STOP_SND_J;
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NextState_prcTxB <= `STOP_SND_J;
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next_USBWireWEn <= 1'b1;
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next_USBWireWEn <= 1'b1;
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next_USBWireData <= `SE0;
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next_USBWireData <= `SE0;
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next_USBWireCtrl <= `DRIVE;
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next_USBWireCtrl <= `DRIVE;
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end
|
end
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end
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`STOP_W_RDY3:
|
`STOP_W_RDY3:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `STOP_SND_IDLE;
|
NextState_prcTxB <= `STOP_SND_IDLE;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
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next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
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next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
end
|
end
|
end
|
|
`STOP_W_RDY4:
|
`STOP_W_RDY4:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `STOP_FIN;
|
NextState_prcTxB <= `STOP_FIN;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireCtrl <= `TRI_STATE;
|
end
|
end
|
end
|
|
`LS_START_SND_IDLE3:
|
`LS_START_SND_IDLE3:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
NextState_prcTxB <= `LS_START_W_RDY2;
|
NextState_prcTxB <= `LS_START_W_RDY2;
|
end
|
end
|
| Line 378... |
Line 349... |
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
NextState_prcTxB <= `LS_START_W_RDY3;
|
NextState_prcTxB <= `LS_START_W_RDY3;
|
end
|
end
|
`LS_START_SND_IDLE1:
|
`LS_START_SND_IDLE1:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `LS_START_SND_IDLE2;
|
NextState_prcTxB <= `LS_START_SND_IDLE2;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireCtrl <= `TRI_STATE;
|
end
|
end
|
end
|
|
`LS_START_SND_IDLE2:
|
`LS_START_SND_IDLE2:
|
begin
|
begin
|
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
NextState_prcTxB <= `LS_START_W_RDY1;
|
NextState_prcTxB <= `LS_START_W_RDY1;
|
end
|
end
|
| Line 399... |
Line 368... |
next_USBWireWEn <= 1'b0;
|
next_USBWireWEn <= 1'b0;
|
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
|
NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
|
next_i <= 4'h0;
|
next_i <= 4'h0;
|
end
|
end
|
`LS_START_W_RDY1:
|
`LS_START_W_RDY1:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `LS_START_SND_IDLE3;
|
NextState_prcTxB <= `LS_START_SND_IDLE3;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireCtrl <= `TRI_STATE;
|
end
|
end
|
end
|
|
`LS_START_W_RDY2:
|
`LS_START_W_RDY2:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `LS_START_SND_J1;
|
NextState_prcTxB <= `LS_START_SND_J1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `TRI_STATE;
|
next_USBWireCtrl <= `TRI_STATE;
|
end
|
end
|
end
|
|
`LS_START_W_RDY3:
|
`LS_START_W_RDY3:
|
begin
|
|
if (USBWireRdy == 1'b1)
|
if (USBWireRdy == 1'b1)
|
begin
|
begin
|
NextState_prcTxB <= `LS_START_FIN;
|
NextState_prcTxB <= `LS_START_FIN;
|
//Drive the first JBit
|
//Drive the first JBit
|
next_USBWireWEn <= 1'b1;
|
next_USBWireWEn <= 1'b1;
|
next_USBWireData <= JBit;
|
next_USBWireData <= JBit;
|
next_USBWireCtrl <= `DRIVE;
|
next_USBWireCtrl <= `DRIVE;
|
end
|
end
|
end
|
|
endcase
|
endcase
|
end
|
end
|
|
|
|
//----------------------------------
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : prcTxB_CurrentState
|
if (rst)
|
if (rst)
|
CurrState_prcTxB <= `START_PTBY;
|
CurrState_prcTxB <= `START_PTBY;
|
else
|
else
|
CurrState_prcTxB <= NextState_prcTxB;
|
CurrState_prcTxB <= NextState_prcTxB;
|
end
|
end
|
|
|
|
//----------------------------------
|
// Registered outputs logic
|
// Registered outputs logic
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : prcTxB_RegOutput
|
if (rst)
|
if (rst)
|
begin
|
begin
|
processTxByteRdy <= 1'b0;
|
|
USBWireData <= 2'b00;
|
|
USBWireCtrl <= `TRI_STATE;
|
|
USBWireReq <= 1'b0;
|
|
USBWireWEn <= 1'b0;
|
|
USBWireFullSpeedRate <= 1'b0;
|
|
i <= 4'h0;
|
i <= 4'h0;
|
TxByte <= 8'h00;
|
TxByte <= 8'h00;
|
TxByteCtrl <= 8'h00;
|
TxByteCtrl <= 8'h00;
|
TXLineState <= 2'b0;
|
TXLineState <= 2'b0;
|
TXOneCount <= 4'h0;
|
TXOneCount <= 4'h0;
|
TxByteFullSpeedRate <= 1'b0;
|
TxByteFullSpeedRate <= 1'b0;
|
|
processTxByteRdy <= 1'b0;
|
|
USBWireData <= 2'b00;
|
|
USBWireCtrl <= `TRI_STATE;
|
|
USBWireReq <= 1'b0;
|
|
USBWireWEn <= 1'b0;
|
|
USBWireFullSpeedRate <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
processTxByteRdy <= next_processTxByteRdy;
|
|
USBWireData <= next_USBWireData;
|
|
USBWireCtrl <= next_USBWireCtrl;
|
|
USBWireReq <= next_USBWireReq;
|
|
USBWireWEn <= next_USBWireWEn;
|
|
USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
|
|
i <= next_i;
|
i <= next_i;
|
TxByte <= next_TxByte;
|
TxByte <= next_TxByte;
|
TxByteCtrl <= next_TxByteCtrl;
|
TxByteCtrl <= next_TxByteCtrl;
|
TXLineState <= next_TXLineState;
|
TXLineState <= next_TXLineState;
|
TXOneCount <= next_TXOneCount;
|
TXOneCount <= next_TXOneCount;
|
TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
|
TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
|
|
processTxByteRdy <= next_processTxByteRdy;
|
|
USBWireData <= next_USBWireData;
|
|
USBWireCtrl <= next_USBWireCtrl;
|
|
USBWireReq <= next_USBWireReq;
|
|
USBWireWEn <= next_USBWireWEn;
|
|
USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
