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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: processTxByte.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
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module processTxByte (clk, fullSpeedRate, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
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input clk;
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input clk;
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input fullSpeedRate;
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input [1:0]JBit;
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input [1:0]JBit;
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input [1:0]KBit;
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input [1:0]KBit;
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input processTxByteWEn;
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input processTxByteWEn;
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input rst;
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input rst;
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input [7:0]TxByteCtrlIn;
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input [7:0]TxByteCtrlIn;
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Line 62... |
output [1:0]USBWireData;
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output [1:0]USBWireData;
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output USBWireReq;
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output USBWireReq;
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output USBWireWEn;
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output USBWireWEn;
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wire clk;
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wire clk;
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wire fullSpeedRate;
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wire [1:0]JBit;
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wire [1:0]JBit;
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wire [1:0]KBit;
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wire [1:0]KBit;
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reg processTxByteRdy, next_processTxByteRdy;
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reg processTxByteRdy, next_processTxByteRdy;
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wire processTxByteWEn;
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wire processTxByteWEn;
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wire rst;
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wire rst;
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Line 86... |
reg [1:0]TXLineState, next_TXLineState;
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reg [1:0]TXLineState, next_TXLineState;
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reg [3:0]TXOneCount, next_TXOneCount;
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reg [3:0]TXOneCount, next_TXOneCount;
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// BINARY ENCODED state machine: prcTxB
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// BINARY ENCODED state machine: prcTxB
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// State codes definitions:
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// State codes definitions:
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`define START_PTBY 4'b0000
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`define START_PTBY 5'b00000
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`define PTBY_WAIT_EN 4'b0001
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`define PTBY_WAIT_EN 5'b00001
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`define SEND_BYTE_UPDATE_BYTE 4'b0010
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`define SEND_BYTE_UPDATE_BYTE 5'b00010
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`define SEND_BYTE_WAIT_RDY 4'b0011
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`define SEND_BYTE_WAIT_RDY 5'b00011
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`define SEND_BYTE_CHK 4'b0100
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`define SEND_BYTE_CHK 5'b00100
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`define SEND_BYTE_BIT_STUFF 4'b0101
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`define SEND_BYTE_BIT_STUFF 5'b00101
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`define SEND_BYTE_WAIT_RDY2 4'b0110
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`define SEND_BYTE_WAIT_RDY2 5'b00110
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`define SEND_BYTE_CHK_FIN 4'b0111
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`define SEND_BYTE_CHK_FIN 5'b00111
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`define PTBY_WAIT_GNT 4'b1000
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`define PTBY_WAIT_GNT 5'b01000
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`define STOP_SND_SE0_2 4'b1001
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`define STOP_SND_SE0_2 5'b01001
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`define STOP_SND_SE0_1 4'b1010
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`define STOP_SND_SE0_1 5'b01010
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`define STOP_CHK 4'b1011
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`define STOP_CHK 5'b01011
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`define STOP_SND_J 4'b1100
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`define STOP_SND_J 5'b01100
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`define STOP_SND_IDLE 4'b1101
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`define STOP_SND_IDLE 5'b01101
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`define STOP_FIN 4'b1110
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`define STOP_FIN 5'b01110
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`define WAIT_RDY_WIRE 5'b01111
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`define WAIT_RDY_PKT 5'b10000
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`define LS_START_SND_IDLE3 5'b10001
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`define LS_START_SND_J1 5'b10010
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`define LS_START_SND_IDLE1 5'b10011
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`define LS_START_SND_IDLE2 5'b10100
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`define LS_START_FIN 5'b10101
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reg [3:0]CurrState_prcTxB, NextState_prcTxB;
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reg [4:0]CurrState_prcTxB, NextState_prcTxB;
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// Machine: prcTxB
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// Machine: prcTxB
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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end
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end
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`PTBY_WAIT_GNT:
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`PTBY_WAIT_GNT:
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begin
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begin
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if (USBWireGnt == 1'b1)
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if (USBWireGnt == 1'b1)
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begin
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begin
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NextState_prcTxB <= `WAIT_RDY_WIRE;
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end
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end
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`WAIT_RDY_WIRE:
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begin
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if ((USBWireRdy == 1'b1) && (fullSpeedRate == 1'b0))
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begin
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NextState_prcTxB <= `LS_START_SND_IDLE1;
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end
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else if (USBWireRdy == 1'b1)
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begin
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NextState_prcTxB <= `WAIT_RDY_PKT;
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//actively drive the first J bit
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next_USBWireData <= JBit;
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next_USBWireCtrl <= `DRIVE;
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next_USBWireWEn <= 1'b1;
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end
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end
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`WAIT_RDY_PKT:
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begin
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next_USBWireWEn <= 1'b0;
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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next_i <= 4'h0;
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next_i <= 4'h0;
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end
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end
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end
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`SEND_BYTE_UPDATE_BYTE:
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`SEND_BYTE_UPDATE_BYTE:
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begin
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begin
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next_i <= i + 1'b1;
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next_i <= i + 1'b1;
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next_TxByte <= {1'b0, TxByte[7:1] };
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next_TxByte <= {1'b0, TxByte[7:1] };
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if (TxByte[0] == 1'b1) //If this bit is 1, then
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if (TxByte[0] == 1'b1) //If this bit is 1, then
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next_USBWireWEn <= 1'b0;
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next_USBWireWEn <= 1'b0;
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next_USBWireReq <= 1'b0;
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next_USBWireReq <= 1'b0;
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//release the wire
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//release the wire
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NextState_prcTxB <= `PTBY_WAIT_EN;
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NextState_prcTxB <= `PTBY_WAIT_EN;
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end
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end
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`LS_START_SND_IDLE3:
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begin
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next_USBWireWEn <= 1'b0;
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if (USBWireRdy == 1'b1)
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begin
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NextState_prcTxB <= `LS_START_SND_J1;
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next_USBWireWEn <= 1'b1;
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next_USBWireData <= JBit;
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next_USBWireCtrl <= `TRI_STATE;
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end
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end
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`LS_START_SND_J1:
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begin
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next_USBWireWEn <= 1'b0;
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if (USBWireRdy == 1'b1)
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begin
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NextState_prcTxB <= `LS_START_FIN;
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//Drive the first JBit
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next_USBWireWEn <= 1'b1;
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next_USBWireData <= JBit;
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next_USBWireCtrl <= `DRIVE;
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end
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end
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`LS_START_SND_IDLE1:
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begin
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if (USBWireRdy == 1'b1)
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begin
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NextState_prcTxB <= `LS_START_SND_IDLE2;
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next_USBWireWEn <= 1'b1;
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next_USBWireData <= JBit;
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next_USBWireCtrl <= `TRI_STATE;
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end
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end
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`LS_START_SND_IDLE2:
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begin
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next_USBWireWEn <= 1'b0;
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if (USBWireRdy == 1'b1)
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begin
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NextState_prcTxB <= `LS_START_SND_IDLE3;
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next_USBWireWEn <= 1'b1;
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next_USBWireData <= JBit;
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next_USBWireCtrl <= `TRI_STATE;
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end
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end
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`LS_START_FIN:
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begin
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next_USBWireWEn <= 1'b0;
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NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
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next_i <= 4'h0;
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end
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endcase
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endcase
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end
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end
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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always @ (posedge clk)
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always @ (posedge clk)
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