| Line 4... |
Line 4... |
//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// ////
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//// Module Description: ////
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//// Module Description: ////
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//// This module reads data from the differential USB data lines
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//// and writes into a 4 entry FIFO. The data is read from
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//// the fifo and output from the module when the higher level
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//// state machine is ready to receive the data.
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//// This module must recover the clock phase from the incoming
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//// USB data. 'sampleCnt' is reset to zero whenever a RX data
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//// edge is detected. Note that due to metastability the data
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//// at the edge may not be registered correctly, but this does
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//// not matter. All that matters is that an edge was detected. The
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//// data will be accurately sampled in the middle of the USB bit
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//// period without metastability issues.
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//// After the edge detect, 'sampleCnt' is incremented at every clock
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//// tick, and when it indicates the middle of a USB bit period
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//// the RX data is sampled and written to the input buffer.
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//// Single clock tick adjustments to 'sampleCnt' can be made at
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//// every RX data edge detect without double sampling the incoming
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//// data. However, the first RX data bit in a packet may cause
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//// 'sampleCnt' to be adjusted by a value greater than a single
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//// clock tick, and this can result in double sampling of the
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//// first data bit a RX packet. This
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//// double sampled data must be rejected by the higher level module.
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//// This is achieved by
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//// qualifying the outgoing data with 'RxWireActive'. Thus
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//// the first data bit in a RX packet may be double sampled
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//// as the clock recovery mechanism synchronizes to 'RxBitsIn'
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//// but the double sampled data will be rejected by the higher
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//// level module.
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////
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////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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////
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////
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//// ////
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//// ////
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| Line 42... |
Line 69... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive);
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module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive, noActivityTimeOutEnable);
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input [1:0] RxBitsIn;
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input [1:0] RxBitsIn;
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output RxDataInTick;
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output RxDataInTick;
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input SIERxRdyIn;
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input SIERxRdyIn;
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input clk;
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input clk;
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input fullSpeedRate;
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input fullSpeedRate;
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| Line 54... |
Line 81... |
input TxWireActiveDrive;
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input TxWireActiveDrive;
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output [1:0] RxBitsOut;
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output [1:0] RxBitsOut;
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output SIERxWEn;
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output SIERxWEn;
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output noActivityTimeOut;
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output noActivityTimeOut;
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output RxWireActive;
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output RxWireActive;
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input noActivityTimeOutEnable;
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wire [1:0] RxBitsIn;
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wire [1:0] RxBitsIn;
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reg RxDataInTick;
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reg RxDataInTick;
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wire SIERxRdyIn;
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wire SIERxRdyIn;
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wire clk;
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wire clk;
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| Line 65... |
Line 93... |
wire rst;
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wire rst;
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reg [1:0] RxBitsOut;
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reg [1:0] RxBitsOut;
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reg SIERxWEn;
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reg SIERxWEn;
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reg noActivityTimeOut;
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reg noActivityTimeOut;
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reg RxWireActive;
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reg RxWireActive;
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wire noActivityTimeOutEnable;
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// local registers
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// local registers
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reg [2:0]buffer0;
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reg [2:0]buffer0;
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reg [2:0]buffer1;
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reg [2:0]buffer1;
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reg [2:0]buffer2;
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reg [2:0]buffer2;
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reg [2:0]buffer3;
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reg [2:0]buffer3;
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reg [2:0]bufferCnt;
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reg [2:0]bufferCnt;
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reg [1:0]bufferInIndex;
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reg [1:0]bufferInIndex;
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reg [1:0]bufferOutIndex;
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reg [1:0]bufferOutIndex;
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reg decBufferCnt;
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reg decBufferCnt;
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reg [4:0]i;
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reg [4:0]sampleCnt;
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reg incBufferCnt;
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reg incBufferCnt;
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reg [1:0]oldRxBitsIn;
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reg [1:0]oldRxBitsIn;
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reg [1:0] RxBitsInReg;
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reg [1:0] RxBitsInReg;
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reg [15:0] timeOutCnt;
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reg [15:0] timeOutCnt;
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reg [7:0] rxActiveCnt;
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reg RxWireEdgeDetect;
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reg RxWireEdgeDetect;
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reg RxWireActiveReg1;
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reg RxWireActiveReg;
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reg RxWireActiveReg2;
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reg RxWireActiveReg2;
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|
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// buffer output state machine state codes:
|
// buffer output state machine state codes:
|
`define WAIT_BUFFER_NOT_EMPTY 2'b00
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`define WAIT_BUFFER_NOT_EMPTY 2'b00
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`define WAIT_SIE_RX_READY 2'b01
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`define WAIT_SIE_RX_READY 2'b01
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| Line 112... |
Line 142... |
//Perform line rate clock recovery
|
//Perform line rate clock recovery
|
//Recover the wire data, and store data to buffer
|
//Recover the wire data, and store data to buffer
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rst == 1'b1)
|
if (rst == 1'b1)
|
begin
|
begin
|
i <= 5'b00000;
|
sampleCnt <= 5'b00000;
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incBufferCnt <= 1'b0;
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incBufferCnt <= 1'b0;
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bufferInIndex <= 2'b00;
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bufferInIndex <= 2'b00;
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buffer0 <= 3'b000;
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buffer0 <= 3'b000;
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buffer1 <= 3'b000;
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buffer1 <= 3'b000;
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buffer2 <= 3'b000;
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buffer2 <= 3'b000;
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buffer3 <= 3'b000;
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buffer3 <= 3'b000;
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RxDataInTick <= 1'b0;
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RxDataInTick <= 1'b0;
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RxWireEdgeDetect <= 1'b0;
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RxWireEdgeDetect <= 1'b0;
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RxWireActiveReg1 <= 1'b0;
|
RxWireActiveReg <= 1'b0;
|
RxWireActiveReg2 <= 1'b0;
|
RxWireActiveReg2 <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
RxWireActiveReg2 <= RxWireActiveReg1; //Delay RxWireActiveReg1 until after i has been reset
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RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset
|
RxBitsInReg <= RxBitsIn; //sync incoming data to local clock to avoid metastability issues
|
RxBitsInReg <= RxBitsIn;
|
incBufferCnt <= 1'b0; //default value
|
|
oldRxBitsIn <= RxBitsInReg;
|
oldRxBitsIn <= RxBitsInReg;
|
if ( (TxWireActiveDrive == 1'b0) && (oldRxBitsIn != RxBitsInReg)) begin //if edge detected then
|
incBufferCnt <= 1'b0; //default value
|
i <= 5'b00000; //reset the counter
|
if ( (TxWireActiveDrive == 1'b0) && (RxBitsIn != RxBitsInReg)) begin //if edge detected then
|
|
sampleCnt <= 5'b00000;
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RxWireEdgeDetect <= 1'b1; // flag receive activity
|
RxWireEdgeDetect <= 1'b1; // flag receive activity
|
RxWireActiveReg1 <= 1'b1;
|
RxWireActiveReg <= 1'b1;
|
|
rxActiveCnt <= 8'h00;
|
end
|
end
|
else begin
|
else begin
|
i <= i + 1'b1;
|
sampleCnt <= sampleCnt + 1'b1;
|
RxWireEdgeDetect <= 1'b0;
|
RxWireEdgeDetect <= 1'b0;
|
|
rxActiveCnt <= rxActiveCnt + 1'b1;
|
|
//clear 'RxWireActiveReg' if no RX transitions for RX_EDGE_DET_TOUT USB bit periods
|
|
if ( (fullSpeedRate == 1'b1 && rxActiveCnt == `RX_EDGE_DET_TOUT * `FS_OVER_SAMPLE_RATE)
|
|
|| (fullSpeedRate == 1'b0 && rxActiveCnt == `RX_EDGE_DET_TOUT * `LS_OVER_SAMPLE_RATE) )
|
|
RxWireActiveReg <= 1'b0;
|
end
|
end
|
if (noActivityTimeOut == 1'b1)
|
if ( (fullSpeedRate == 1'b1 && sampleCnt[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && sampleCnt == 5'b10000) )
|
RxWireActiveReg1 <= 1'b0;
|
|
if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
|
|
begin
|
begin
|
RxDataInTick <= !RxDataInTick;
|
RxDataInTick <= !RxDataInTick;
|
if (TxWireActiveDrive != 1'b1) //do not read wire data when transmitter is active
|
if (TxWireActiveDrive != 1'b1) //do not read wire data when transmitter is active
|
begin
|
begin
|
incBufferCnt <= 1'b1;
|
incBufferCnt <= 1'b1;
|
bufferInIndex <= bufferInIndex + 1'b1;
|
bufferInIndex <= bufferInIndex + 1'b1;
|
case (bufferInIndex)
|
case (bufferInIndex)
|
2'b00 : buffer0 <= {RxWireActiveReg2, RxBitsInReg};
|
2'b00 : buffer0 <= {RxWireActiveReg2, oldRxBitsIn};
|
2'b01 : buffer1 <= {RxWireActiveReg2, RxBitsInReg};
|
2'b01 : buffer1 <= {RxWireActiveReg2, oldRxBitsIn};
|
2'b10 : buffer2 <= {RxWireActiveReg2, RxBitsInReg};
|
2'b10 : buffer2 <= {RxWireActiveReg2, oldRxBitsIn};
|
2'b11 : buffer3 <= {RxWireActiveReg2, RxBitsInReg};
|
2'b11 : buffer3 <= {RxWireActiveReg2, oldRxBitsIn};
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
| Line 203... |
Line 237... |
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//generate time out flag if no tx or rx activity
|
//generate 'noActivityTimeOut' pulse if no tx or rx activity for RX_PACKET_TOUT USB bit periods
|
|
//'noActivityTimeOut' pulse can only be generated when the host or slave getPacket
|
|
//process enables via 'noActivityTimeOutEnable' signal
|
|
//'noActivityTimeOut' pulse is used by host and slave getPacket processes to determine if
|
|
//there has been a response time out.
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if (rst) begin
|
if (rst) begin
|
timeOutCnt <= 16'h0000;
|
timeOutCnt <= 16'h0000;
|
noActivityTimeOut <= 1'b0;
|
noActivityTimeOut <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1)
|
if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1 || noActivityTimeOutEnable == 1'b0)
|
timeOutCnt <= 16'h0000;
|
timeOutCnt <= 16'h0000;
|
else
|
else
|
timeOutCnt <= timeOutCnt + 1'b1;
|
timeOutCnt <= timeOutCnt + 1'b1;
|
if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
|
if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
|
|| (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
|
|| (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
|
| Line 222... |
Line 260... |
else
|
else
|
noActivityTimeOut <= 1'b0;
|
noActivityTimeOut <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
