| Line 113... |
Line 113... |
reg [15:0] timeOutCnt;
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reg [15:0] timeOutCnt;
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reg [7:0] rxActiveCnt;
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reg [7:0] rxActiveCnt;
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reg RxWireEdgeDetect;
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reg RxWireEdgeDetect;
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reg RxWireActiveReg;
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reg RxWireActiveReg;
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reg RxWireActiveReg2;
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reg RxWireActiveReg2;
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reg [1:0] RxBitsInSyncReg1;
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reg [1:0] RxBitsInSyncReg2;
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// buffer output state machine state codes:
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// buffer output state machine state codes:
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`define WAIT_BUFFER_NOT_EMPTY 2'b00
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`define WAIT_BUFFER_NOT_EMPTY 2'b00
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`define WAIT_SIE_RX_READY 2'b01
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`define WAIT_SIE_RX_READY 2'b01
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`define SIE_RX_WRITE 2'b10
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`define SIE_RX_WRITE 2'b10
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// re-synchronize incoming bits
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always @(posedge clk) begin
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RxBitsInSyncReg1 <= RxBitsIn;
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RxBitsInSyncReg2 <= RxBitsInSyncReg1;
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end
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reg [1:0] bufferOutStMachCurrState;
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reg [1:0] bufferOutStMachCurrState;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rst == 1'b1)
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if (rst == 1'b1)
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| Line 156... |
Line 164... |
RxWireActiveReg <= 1'b0;
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RxWireActiveReg <= 1'b0;
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RxWireActiveReg2 <= 1'b0;
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RxWireActiveReg2 <= 1'b0;
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end
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end
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else begin
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else begin
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RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset
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RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset
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RxBitsInReg <= RxBitsIn;
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RxBitsInReg <= RxBitsInSyncReg2;
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oldRxBitsIn <= RxBitsInReg;
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oldRxBitsIn <= RxBitsInReg;
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incBufferCnt <= 1'b0; //default value
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incBufferCnt <= 1'b0; //default value
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if ( (TxWireActiveDrive == 1'b0) && (RxBitsIn != RxBitsInReg)) begin //if edge detected then
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if ( (TxWireActiveDrive == 1'b0) && (RxBitsInSyncReg2 != RxBitsInReg)) begin //if edge detected then
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sampleCnt <= 5'b00000;
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sampleCnt <= 5'b00000;
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RxWireEdgeDetect <= 1'b1; // flag receive activity
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RxWireEdgeDetect <= 1'b1; // flag receive activity
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RxWireActiveReg <= 1'b1;
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RxWireActiveReg <= 1'b1;
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rxActiveCnt <= 8'h00;
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rxActiveCnt <= 8'h00;
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end
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end
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