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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: readUSBWireData.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2004/10/11 04:01:01 sfielding
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// Created
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//
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//
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, disableWireRead, clk, rst);
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module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut);
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input [1:0] RxBitsIn;
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input [1:0] RxBitsIn;
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output RxDataInTick;
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output RxDataInTick;
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input SIERxRdyIn;
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input SIERxRdyIn;
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input clk;
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input clk;
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input fullSpeedRate;
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input fullSpeedRate;
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input rst;
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input rst;
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input disableWireRead;
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input TxWireActiveDrive;
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output [1:0] RxBitsOut;
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output [1:0] RxBitsOut;
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output SIERxWEn;
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output SIERxWEn;
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output noActivityTimeOut;
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wire [1:0] RxBitsIn;
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wire [1:0] RxBitsIn;
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reg RxDataInTick;
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reg RxDataInTick;
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wire SIERxRdyIn;
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wire SIERxRdyIn;
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wire clk;
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wire clk;
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wire fullSpeedRate;
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wire fullSpeedRate;
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wire rst;
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wire rst;
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reg [1:0] RxBitsOut;
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reg [1:0] RxBitsOut;
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reg SIERxWEn;
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reg SIERxWEn;
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reg noActivityTimeOut;
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// local registers
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// local registers
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reg [1:0]buffer0;
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reg [1:0]buffer0;
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reg [1:0]buffer1;
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reg [1:0]buffer1;
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reg [1:0]buffer2;
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reg [1:0]buffer2;
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reg decBufferCnt;
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reg decBufferCnt;
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reg [4:0]i;
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reg [4:0]i;
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reg incBufferCnt;
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reg incBufferCnt;
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reg [1:0]oldRxBitsIn;
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reg [1:0]oldRxBitsIn;
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reg [1:0] RxBitsInReg;
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reg [1:0] RxBitsInReg;
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reg [15:0] timeOutCnt;
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reg RxWireActive;
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// buffer output state machine state codes:
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// buffer output state machine state codes:
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`define WAIT_BUFFER_NOT_EMPTY 2'b00
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`define WAIT_BUFFER_NOT_EMPTY 2'b00
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`define WAIT_SIE_RX_READY 2'b01
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`define WAIT_SIE_RX_READY 2'b01
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`define SIE_RX_WRITE 2'b10
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`define SIE_RX_WRITE 2'b10
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buffer0 <= 2'b00;
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buffer0 <= 2'b00;
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buffer1 <= 2'b00;
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buffer1 <= 2'b00;
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buffer2 <= 2'b00;
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buffer2 <= 2'b00;
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buffer3 <= 2'b00;
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buffer3 <= 2'b00;
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RxDataInTick <= 1'b0;
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RxDataInTick <= 1'b0;
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RxWireActive <= 1'b0;
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end
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end
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else begin
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else begin
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RxBitsInReg <= RxBitsIn; //sync to local clock to avoid metastability issues
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RxBitsInReg <= RxBitsIn; //sync to local clock to avoid metastability issues
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incBufferCnt <= 1'b0; //default value
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incBufferCnt <= 1'b0; //default value
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oldRxBitsIn <= RxBitsInReg;
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oldRxBitsIn <= RxBitsInReg;
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if (oldRxBitsIn != RxBitsInReg) //if edge detected then
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if (oldRxBitsIn != RxBitsInReg) begin //if edge detected then
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i <= 5'b00000; //reset the counter
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i <= 5'b00000; //reset the counter
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else
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RxWireActive <= 1'b1; // flag receive activity
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end
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else begin
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i <= i + 1'b1;
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i <= i + 1'b1;
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RxWireActive <= 1'b0;
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end
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if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
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if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
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begin
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begin
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RxDataInTick <= !RxDataInTick;
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RxDataInTick <= !RxDataInTick;
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if (disableWireRead != 1'b1) //do not read wire data when transmitter is active
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if (TxWireActiveDrive != 1'b1) //do not read wire data when transmitter is active
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begin
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begin
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incBufferCnt <= 1'b1;
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incBufferCnt <= 1'b1;
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bufferInIndex <= bufferInIndex + 1'b1;
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bufferInIndex <= bufferInIndex + 1'b1;
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case (bufferInIndex)
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case (bufferInIndex)
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2'b00 : buffer0 <= RxBitsInReg;
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2'b00 : buffer0 <= RxBitsInReg;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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//generate time out flag if no tx or rx activity
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always @(posedge clk) begin
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if (rst) begin
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timeOutCnt <= 16'h0000;
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noActivityTimeOut <= 1'b0;
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end
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else begin
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if (TxWireActiveDrive == 1'b1 || RxWireActive == 1'b1)
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timeOutCnt <= 16'h0000;
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else
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timeOutCnt <= timeOutCnt + 1'b1;
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//if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)
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if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
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|| (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
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//if (timeOutCnt == 16'h200) //temporary hack
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noActivityTimeOut <= 1'b1;
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else
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noActivityTimeOut <= 1'b0;
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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