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// File : ../RTL/serialInterfaceEngine/siereceiver.v
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// Generated : 10/06/06 19:35:30
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// From : ../RTL/serialInterfaceEngine/siereceiver.asf
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// By : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// SIEReceiver
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//// SIEReceiver
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module SIEReceiver (clk, connectState, rst, RxWireDataIn, RxWireDataWEn);
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module SIEReceiver (RxWireDataIn, RxWireDataWEn, clk, connectState, rst);
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input clk;
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input rst;
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input [1:0]RxWireDataIn;
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input [1:0]RxWireDataIn;
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input RxWireDataWEn;
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input RxWireDataWEn;
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input clk;
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input rst;
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output [1:0]connectState;
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output [1:0]connectState;
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wire [1:0] RxWireDataIn;
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wire RxWireDataWEn;
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wire clk;
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wire clk;
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reg [1:0]connectState, next_connectState;
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reg [1:0]connectState, next_connectState;
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wire rst;
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wire rst;
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wire [1:0]RxWireDataIn;
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wire RxWireDataWEn;
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// diagram signals declarations
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// diagram signals declarations
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reg [1:0]RxBits, next_RxBits;
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reg [3:0]RXStMachCurrState, next_RXStMachCurrState;
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reg [3:0]RXStMachCurrState, next_RXStMachCurrState;
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reg [7:0]RXWaitCount, next_RXWaitCount;
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reg [7:0]RXWaitCount, next_RXWaitCount;
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reg [1:0]RxBits, next_RxBits;
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// BINARY ENCODED state machine: rcvr
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// BINARY ENCODED state machine: rcvr
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// State codes definitions:
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// State codes definitions:
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`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
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`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
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`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
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`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
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`define START_SRX 4'b0101
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`define START_SRX 4'b0101
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`define FS_CONN_CHK_RX_BITS1 4'b0110
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`define FS_CONN_CHK_RX_BITS1 4'b0110
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`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
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`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
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`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
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`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
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reg [3:0]CurrState_rcvr, NextState_rcvr;
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reg [3:0] CurrState_rcvr;
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reg [3:0] NextState_rcvr;
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//--------------------------------------------------------------------
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// Machine: rcvr
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// Machine: rcvr
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//--------------------------------------------------------------------
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (RXWaitCount or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or CurrState_rcvr)
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// Next State Logic (combinatorial)
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begin
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//----------------------------------
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always @ (RxWireDataIn or RxBits or RXWaitCount or RxWireDataWEn or RXStMachCurrState or connectState or CurrState_rcvr)
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begin : rcvr_NextState
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NextState_rcvr <= CurrState_rcvr;
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NextState_rcvr <= CurrState_rcvr;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_RxBits <= RxBits;
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next_RXStMachCurrState <= RXStMachCurrState;
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next_RXWaitCount <= RXWaitCount;
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next_RXWaitCount <= RXWaitCount;
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next_connectState <= connectState;
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next_connectState <= connectState;
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next_RXStMachCurrState <= RXStMachCurrState;
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case (CurrState_rcvr)
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next_RxBits <= RxBits;
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case (CurrState_rcvr) // synopsys parallel_case full_case
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`WAIT_BIT:
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`WAIT_BIT:
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begin
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if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
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if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
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begin
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begin
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NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
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NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
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next_RxBits <= RxWireDataIn;
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next_RxBits <= RxWireDataIn;
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end
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end
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
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begin
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begin
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NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
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NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
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next_RxBits <= RxWireDataIn;
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next_RxBits <= RxWireDataIn;
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end
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end
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end
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`START_SRX:
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`START_SRX:
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begin
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begin
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next_RXStMachCurrState <= `DISCONNECT_ST;
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next_RXStMachCurrState <= `DISCONNECT_ST;
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next_RXWaitCount <= 8'h00;
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next_RXWaitCount <= 8'h00;
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next_connectState <= `DISCONNECT;
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next_connectState <= `DISCONNECT;
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next_RxBits <= 2'b00;
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next_RxBits <= 2'b00;
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NextState_rcvr <= `WAIT_BIT;
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NextState_rcvr <= `WAIT_BIT;
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end
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end
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`DISCNCT_CHK_RXBITS:
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`DISCNCT_CHK_RXBITS:
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begin
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if (RxBits == `ZERO_ONE)
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if (RxBits == `ZERO_ONE)
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begin
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begin
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NextState_rcvr <= `WAIT_BIT;
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NextState_rcvr <= `WAIT_BIT;
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next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
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next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
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next_RXWaitCount <= 8'h00;
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next_RXWaitCount <= 8'h00;
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NextState_rcvr <= `WAIT_BIT;
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NextState_rcvr <= `WAIT_BIT;
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next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
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next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
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next_RXWaitCount <= 8'h00;
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next_RXWaitCount <= 8'h00;
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end
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end
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else
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else
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begin
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NextState_rcvr <= `WAIT_BIT;
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NextState_rcvr <= `WAIT_BIT;
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end
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end
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`WAIT_FS_CONN_CHK_RX_BITS:
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`WAIT_FS_CONN_CHK_RX_BITS:
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begin
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begin
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if (RxBits == `ONE_ZERO)
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if (RxBits == `ONE_ZERO)
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begin
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begin
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next_RXWaitCount <= RXWaitCount + 1'b1;
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next_RXWaitCount <= RXWaitCount + 1'b1;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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//----------------------------------
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin : rcvr_CurrentState
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if (rst)
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if (rst)
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CurrState_rcvr <= `START_SRX;
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CurrState_rcvr <= `START_SRX;
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else
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else
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CurrState_rcvr <= NextState_rcvr;
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CurrState_rcvr <= NextState_rcvr;
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end
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end
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//----------------------------------
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// Registered outputs logic
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin : rcvr_RegOutput
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if (rst)
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if (rst)
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begin
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begin
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connectState <= `DISCONNECT;
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RXWaitCount <= 8'h00;
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RXStMachCurrState <= `DISCONNECT_ST;
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RXStMachCurrState <= `DISCONNECT_ST;
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RXWaitCount <= 8'h00;
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RxBits <= 2'b00;
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RxBits <= 2'b00;
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connectState <= `DISCONNECT;
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end
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end
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else
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else
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begin
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begin
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connectState <= next_connectState;
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RXWaitCount <= next_RXWaitCount;
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RXStMachCurrState <= next_RXStMachCurrState;
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RXStMachCurrState <= next_RXStMachCurrState;
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RXWaitCount <= next_RXWaitCount;
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RxBits <= next_RxBits;
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RxBits <= next_RxBits;
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connectState <= next_connectState;
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end
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end
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end
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end
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endmodule
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endmodule
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