| Line 40... |
Line 40... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: siereceiver.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module SIEReceiver (clk, connectState, processRxBitRdyIn, processRxBitsWEn, rst, RxBitsOut, RxWireDataIn, RxWireDataWEn, SIERxRdyOut);
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module SIEReceiver (clk, connectState, rst, RxWireDataIn, RxWireDataWEn);
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input clk;
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input clk;
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input processRxBitRdyIn;
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input rst;
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input rst;
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input [1:0]RxWireDataIn;
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input [1:0]RxWireDataIn;
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input RxWireDataWEn;
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input RxWireDataWEn;
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output [1:0]connectState;
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output [1:0]connectState;
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output processRxBitsWEn;
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output [1:0]RxBitsOut;
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output SIERxRdyOut;
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wire clk;
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wire clk;
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reg [1:0]connectState, next_connectState;
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reg [1:0]connectState, next_connectState;
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wire processRxBitRdyIn;
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reg processRxBitsWEn, next_processRxBitsWEn;
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wire rst;
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wire rst;
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reg [1:0]RxBitsOut, next_RxBitsOut;
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wire [1:0]RxWireDataIn;
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wire [1:0]RxWireDataIn;
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wire RxWireDataWEn;
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wire RxWireDataWEn;
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reg SIERxRdyOut, next_SIERxRdyOut;
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// diagram signals declarations
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// diagram signals declarations
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reg [1:0]RxBits, next_RxBits;
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reg [1:0]RxBits, next_RxBits;
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reg [3:0]RXStMachCurrState, next_RXStMachCurrState;
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reg [3:0]RXStMachCurrState, next_RXStMachCurrState;
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reg [7:0]RXWaitCount, next_RXWaitCount;
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reg [7:0]RXWaitCount, next_RXWaitCount;
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| Line 84... |
Line 70... |
`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
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`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
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`define LS_CONN_CHK_RX_BITS 4'b0010
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`define LS_CONN_CHK_RX_BITS 4'b0010
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`define DISCNCT_CHK_RXBITS 4'b0011
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`define DISCNCT_CHK_RXBITS 4'b0011
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`define WAIT_BIT 4'b0100
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`define WAIT_BIT 4'b0100
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`define START_SRX 4'b0101
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`define START_SRX 4'b0101
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`define LS_CONN_PROC_RX_BITS 4'b0110
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`define FS_CONN_CHK_RX_BITS1 4'b0110
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`define FS_CONN_CHK_RX_BITS1 4'b0111
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`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
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`define WAIT_LS_DIS_CHK_RX_BITS 4'b1000
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`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
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`define WAIT_LS_DIS_PROC_RX_BITS 4'b1001
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`define WAIT_FS_DIS_PROC_RX_BITS2 4'b1010
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`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1011
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`define FS_CONN_PROC_RX_BITS1 4'b1100
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reg [3:0]CurrState_rcvr, NextState_rcvr;
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reg [3:0]CurrState_rcvr, NextState_rcvr;
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// Machine: rcvr
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// Machine: rcvr
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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always @ (RXWaitCount or processRxBitRdyIn or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or processRxBitsWEn or RxBitsOut or SIERxRdyOut or CurrState_rcvr)
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always @ (RXWaitCount or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or CurrState_rcvr)
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begin
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begin
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NextState_rcvr <= CurrState_rcvr;
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NextState_rcvr <= CurrState_rcvr;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_RXWaitCount <= RXWaitCount;
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next_RXWaitCount <= RXWaitCount;
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next_connectState <= connectState;
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next_connectState <= connectState;
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next_RXStMachCurrState <= RXStMachCurrState;
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next_RXStMachCurrState <= RXStMachCurrState;
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next_processRxBitsWEn <= processRxBitsWEn;
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next_RxBitsOut <= RxBitsOut;
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next_RxBits <= RxBits;
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next_RxBits <= RxBits;
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next_SIERxRdyOut <= SIERxRdyOut;
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case (CurrState_rcvr) // synopsys parallel_case full_case
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case (CurrState_rcvr) // synopsys parallel_case full_case
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`WAIT_BIT:
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`WAIT_BIT:
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begin
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begin
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if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
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if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
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begin
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begin
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NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
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NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
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next_RxBits <= RxWireDataIn;
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next_RxBits <= RxWireDataIn;
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next_SIERxRdyOut <= 1'b0;
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end
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end
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
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begin
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begin
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NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
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NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
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next_RxBits <= RxWireDataIn;
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next_RxBits <= RxWireDataIn;
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next_SIERxRdyOut <= 1'b0;
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end
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end
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
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begin
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begin
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NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
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NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
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next_RxBits <= RxWireDataIn;
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next_RxBits <= RxWireDataIn;
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next_SIERxRdyOut <= 1'b0;
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end
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end
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
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begin
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begin
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NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
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NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
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next_RxBits <= RxWireDataIn;
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next_RxBits <= RxWireDataIn;
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next_SIERxRdyOut <= 1'b0;
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end
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end
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
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begin
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begin
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NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
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NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
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next_RxBits <= RxWireDataIn;
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next_RxBits <= RxWireDataIn;
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next_SIERxRdyOut <= 1'b0;
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end
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end
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
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begin
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begin
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NextState_rcvr <= `DISCNCT_CHK_RXBITS;
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NextState_rcvr <= `DISCNCT_CHK_RXBITS;
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next_RxBits <= RxWireDataIn;
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next_RxBits <= RxWireDataIn;
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next_SIERxRdyOut <= 1'b0;
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end
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end
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
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else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
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begin
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begin
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NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
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NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
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next_RxBits <= RxWireDataIn;
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next_RxBits <= RxWireDataIn;
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next_SIERxRdyOut <= 1'b0;
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end
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end
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end
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end
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`START_SRX:
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`START_SRX:
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begin
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begin
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next_RXStMachCurrState <= `DISCONNECT_ST;
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next_RXStMachCurrState <= `DISCONNECT_ST;
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next_RXWaitCount <= 8'h00;
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next_RXWaitCount <= 8'h00;
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next_connectState <= `DISCONNECT;
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next_connectState <= `DISCONNECT;
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next_RxBits <= 2'b00;
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next_RxBits <= 2'b00;
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next_RxBitsOut <= 2'b00;
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next_processRxBitsWEn <= 1'b0;
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next_SIERxRdyOut <= 1'b1;
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NextState_rcvr <= `WAIT_BIT;
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NextState_rcvr <= `WAIT_BIT;
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end
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end
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`DISCNCT_CHK_RXBITS:
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`DISCNCT_CHK_RXBITS:
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begin
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begin
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if (RxBits == `ZERO_ONE)
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if (RxBits == `ZERO_ONE)
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begin
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begin
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NextState_rcvr <= `WAIT_BIT;
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NextState_rcvr <= `WAIT_BIT;
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next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
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next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
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next_RXWaitCount <= 8'h00;
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next_RXWaitCount <= 8'h00;
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next_SIERxRdyOut <= 1'b1;
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end
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end
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else if (RxBits == `ONE_ZERO)
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else if (RxBits == `ONE_ZERO)
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begin
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begin
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NextState_rcvr <= `WAIT_BIT;
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NextState_rcvr <= `WAIT_BIT;
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next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
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next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
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next_RXWaitCount <= 8'h00;
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next_RXWaitCount <= 8'h00;
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next_SIERxRdyOut <= 1'b1;
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end
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end
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else
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else
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begin
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begin
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NextState_rcvr <= `WAIT_BIT;
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NextState_rcvr <= `WAIT_BIT;
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next_SIERxRdyOut <= 1'b1;
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end
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end
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end
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end
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`WAIT_FS_CONN_CHK_RX_BITS:
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`WAIT_FS_CONN_CHK_RX_BITS:
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begin
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begin
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if (RxBits == `ONE_ZERO)
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if (RxBits == `ONE_ZERO)
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| Line 204... |
Line 170... |
else
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else
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begin
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begin
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next_RXStMachCurrState <= `DISCONNECT_ST;
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next_RXStMachCurrState <= `DISCONNECT_ST;
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end
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end
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NextState_rcvr <= `WAIT_BIT;
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NextState_rcvr <= `WAIT_BIT;
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next_SIERxRdyOut <= 1'b1;
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end
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end
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`WAIT_LS_CONN_CHK_RX_BITS:
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`WAIT_LS_CONN_CHK_RX_BITS:
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begin
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begin
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if (RxBits == `ZERO_ONE)
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if (RxBits == `ZERO_ONE)
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begin
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begin
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| Line 222... |
Line 187... |
else
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else
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begin
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begin
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next_RXStMachCurrState <= `DISCONNECT_ST;
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next_RXStMachCurrState <= `DISCONNECT_ST;
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end
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end
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NextState_rcvr <= `WAIT_BIT;
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NextState_rcvr <= `WAIT_BIT;
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next_SIERxRdyOut <= 1'b1;
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end
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end
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`LS_CONN_CHK_RX_BITS:
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`LS_CONN_CHK_RX_BITS:
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begin
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begin
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if (processRxBitRdyIn == 1'b1)
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NextState_rcvr <= `WAIT_BIT;
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begin
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NextState_rcvr <= `LS_CONN_PROC_RX_BITS;
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if (RxBits == `SE0)
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if (RxBits == `SE0)
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begin
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begin
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next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
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next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
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next_RXWaitCount <= 0;
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next_RXWaitCount <= 0;
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end
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end
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next_processRxBitsWEn <= 1'b1;
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next_RxBitsOut <= RxBits;
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end
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end
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`LS_CONN_PROC_RX_BITS:
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begin
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next_processRxBitsWEn <= 1'b0;
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NextState_rcvr <= `WAIT_BIT;
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next_SIERxRdyOut <= 1'b1;
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end
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end
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`FS_CONN_CHK_RX_BITS1:
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`FS_CONN_CHK_RX_BITS1:
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begin
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begin
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if (processRxBitRdyIn == 1'b1)
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NextState_rcvr <= `WAIT_BIT;
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begin
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NextState_rcvr <= `FS_CONN_PROC_RX_BITS1;
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if (RxBits == `SE0)
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if (RxBits == `SE0)
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begin
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begin
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next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
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next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
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next_RXWaitCount <= 0;
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next_RXWaitCount <= 0;
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end
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end
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next_processRxBitsWEn <= 1'b1;
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next_RxBitsOut <= RxBits;
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next_SIERxRdyOut <= 1'b1;
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//early indication of ready
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end
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end
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`FS_CONN_PROC_RX_BITS1:
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begin
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next_processRxBitsWEn <= 1'b0;
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NextState_rcvr <= `WAIT_BIT;
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next_SIERxRdyOut <= 1'b1;
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end
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end
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`WAIT_LS_DIS_CHK_RX_BITS:
|
`WAIT_LS_DIS_CHK_RX_BITS:
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begin
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begin
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if (processRxBitRdyIn == 1'b1)
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NextState_rcvr <= `WAIT_BIT;
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begin
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NextState_rcvr <= `WAIT_LS_DIS_PROC_RX_BITS;
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if (RxBits == `SE0)
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if (RxBits == `SE0)
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begin
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begin
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next_RXWaitCount <= RXWaitCount + 1'b1;
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next_RXWaitCount <= RXWaitCount + 1'b1;
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if (RXWaitCount == `DISCONNECT_WAIT_TIME)
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if (RXWaitCount == `DISCONNECT_WAIT_TIME)
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begin
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begin
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| Line 284... |
Line 222... |
end
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end
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else
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else
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begin
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begin
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next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
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next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
|
end
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end
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next_processRxBitsWEn <= 1'b1;
|
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end
|
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end
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`WAIT_LS_DIS_PROC_RX_BITS:
|
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begin
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next_processRxBitsWEn <= 1'b0;
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NextState_rcvr <= `WAIT_BIT;
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next_SIERxRdyOut <= 1'b1;
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end
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`WAIT_FS_DIS_PROC_RX_BITS2:
|
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begin
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next_processRxBitsWEn <= 1'b0;
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NextState_rcvr <= `WAIT_BIT;
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next_SIERxRdyOut <= 1'b1;
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end
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end
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`WAIT_FS_DIS_CHK_RX_BITS2:
|
`WAIT_FS_DIS_CHK_RX_BITS2:
|
begin
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begin
|
if (processRxBitRdyIn == 1'b1)
|
NextState_rcvr <= `WAIT_BIT;
|
begin
|
|
NextState_rcvr <= `WAIT_FS_DIS_PROC_RX_BITS2;
|
|
if (RxBits == `SE0)
|
if (RxBits == `SE0)
|
begin
|
begin
|
next_RXWaitCount <= RXWaitCount + 1'b1;
|
next_RXWaitCount <= RXWaitCount + 1'b1;
|
if (RXWaitCount == `DISCONNECT_WAIT_TIME)
|
if (RXWaitCount == `DISCONNECT_WAIT_TIME)
|
begin
|
begin
|
| Line 317... |
Line 239... |
end
|
end
|
else
|
else
|
begin
|
begin
|
next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
|
next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
|
end
|
end
|
next_processRxBitsWEn <= 1'b1;
|
|
end
|
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
| Line 338... |
Line 258... |
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
begin
|
begin
|
connectState <= `DISCONNECT;
|
connectState <= `DISCONNECT;
|
processRxBitsWEn <= 1'b0;
|
|
RxBitsOut <= 2'b00;
|
|
SIERxRdyOut <= 1'b1;
|
|
RXWaitCount <= 8'h00;
|
RXWaitCount <= 8'h00;
|
RXStMachCurrState <= `DISCONNECT_ST;
|
RXStMachCurrState <= `DISCONNECT_ST;
|
RxBits <= 2'b00;
|
RxBits <= 2'b00;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
connectState <= next_connectState;
|
connectState <= next_connectState;
|
processRxBitsWEn <= next_processRxBitsWEn;
|
|
RxBitsOut <= next_RxBitsOut;
|
|
SIERxRdyOut <= next_SIERxRdyOut;
|
|
RXWaitCount <= next_RXWaitCount;
|
RXWaitCount <= next_RXWaitCount;
|
RXStMachCurrState <= next_RXStMachCurrState;
|
RXStMachCurrState <= next_RXStMachCurrState;
|
RxBits <= next_RxBits;
|
RxBits <= next_RxBits;
|
end
|
end
|
end
|
end
|
