| Line 3... |
Line 3... |
FILE="usbTxWireArbiter.asf"
|
FILE="usbTxWireArbiter.asf"
|
FID=4053e959
|
FID=4053e959
|
LANGUAGE=VERILOG
|
LANGUAGE=VERILOG
|
ENTITY="USBTxWireArbiter"
|
ENTITY="USBTxWireArbiter"
|
FRAMES=ON
|
FRAMES=ON
|
FREEOID=128
|
FREEOID=134
|
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// usbTxWireArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
|
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// usbTxWireArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
|
END
|
END
|
BUNDLES
|
BUNDLES
|
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
|
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
|
B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
|
B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
|
| Line 60... |
Line 60... |
W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\
|
W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\
|
200193,83454 202194,93721 199799,97969 197405,102218\
|
200193,83454 202194,93721 199799,97969 197405,102218\
|
189371,107780 182843,108050 176316,108321 158239,103840\
|
189371,107780 182843,108050 176316,108321 158239,103840\
|
151634,101445 145030,99051 137656,94031 133485,91482
|
151634,101445 145030,99051 137656,94031 133485,91482
|
C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
|
C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
|
A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl) \nbegin\n if (muxSIENotPTXB == 1'b1) \n begin\n USBWireWEn <= SIETxWEn;\n TxBits <= SIETxData;\n TxCtl <= SIETxCtrl;\n end\n else\n begin\n USBWireWEn <= prcTxByteWEn;\n TxBits <= prcTxByteData;\n TxCtl <= prcTxByteCtrl;\n end\nend"
|
A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or\nSIETxFSRate or prcTxByteFSRate) \nbegin\n if (muxSIENotPTXB == 1'b1) \n begin\n USBWireWEn <= SIETxWEn;\n TxBits <= SIETxData;\n TxCtl <= SIETxCtrl;\n TxFSRate <= SIETxFSRate;\n end\n else\n begin\n USBWireWEn <= prcTxByteWEn;\n TxBits <= prcTxByteData;\n TxCtl <= prcTxByteCtrl;\n TxFSRate <= prcTxByteFSRate;\n end\nend"
|
C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
|
C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
|
A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
|
A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
|
W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
|
W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
|
70311,70629 71874,86691 76817,93064 81761,99437\
|
70311,70629 71874,86691 76817,93064 81761,99437\
|
89642,107471 97173,106158 104705,104845 116882,95874\
|
89642,107471 97173,106158 104705,104845 116882,95874\
|
123371,91703
|
123371,91703
|
A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
|
A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
|
L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
|
L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
|
I 95 0 2 Builtin Signal | 187475,230225 "" ""
|
I 95 0 2 Builtin Signal | 187475,230225 "" ""
|
I 111 0 2 Builtin OutPort | 153906,181456 "" ""
|
I 111 0 2 Builtin OutPort | 173058,181792 "" ""
|
L 110 111 0 TEXT "Labels" | 159906,181456 1 0 0 "prcTxByteGnt"
|
L 110 111 0 TEXT "Labels" | 179058,181792 1 0 0 "prcTxByteGnt"
|
I 109 0 2 Builtin InPort | 156447,157894 "" ""
|
I 109 0 2 Builtin InPort | 140655,159238 "" ""
|
L 108 109 0 TEXT "Labels" | 162447,157894 1 0 0 "SIETxReq"
|
L 108 109 0 TEXT "Labels" | 146655,159238 1 0 0 "SIETxReq"
|
I 107 0 2 Builtin InPort | 156216,186076 "" ""
|
I 107 0 2 Builtin InPort | 175368,186412 "" ""
|
L 106 107 0 TEXT "Labels" | 162216,186076 1 0 0 "prcTxByteReq"
|
L 106 107 0 TEXT "Labels" | 181368,186412 1 0 0 "prcTxByteReq"
|
I 105 0 2 Builtin OutPort | 154368,153274 "" ""
|
I 105 0 2 Builtin OutPort | 138576,154618 "" ""
|
L 104 105 0 TEXT "Labels" | 160368,153274 1 0 0 "SIETxGnt"
|
L 104 105 0 TEXT "Labels" | 144576,154618 1 0 0 "SIETxGnt"
|
I 103 0 2 Builtin OutPort | 142325,212440 "" ""
|
I 103 0 2 Builtin OutPort | 142325,212440 "" ""
|
L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
|
L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
|
I 101 0 130 Builtin OutPort | 142556,217291 "" ""
|
I 101 0 130 Builtin OutPort | 142556,217291 "" ""
|
L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
|
L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
|
I 99 0 2 Builtin OutPort | 142787,221911 "" ""
|
I 99 0 2 Builtin OutPort | 142787,221911 "" ""
|
L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
|
L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
|
I 127 0 2 Builtin OutPort | 141972,231298 "" ""
|
I 127 0 2 Builtin OutPort | 141972,231298 "" ""
|
L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
|
L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
|
I 125 0 2 Builtin InPort | 144051,235918 "" ""
|
I 125 0 2 Builtin InPort | 144051,235918 "" ""
|
L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
|
L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
|
I 123 0 2 Builtin InPort | 155985,199705 "" ""
|
I 123 0 2 Builtin InPort | 175137,200041 "" ""
|
L 122 123 0 TEXT "Labels" | 161985,199705 1 0 0 "prcTxByteWEn"
|
L 122 123 0 TEXT "Labels" | 181137,200041 1 0 0 "prcTxByteWEn"
|
I 121 0 2 Builtin InPort | 155985,195316 "" ""
|
I 121 0 2 Builtin InPort | 175137,195652 "" ""
|
L 120 121 0 TEXT "Labels" | 161985,195316 1 0 0 "prcTxByteCtrl"
|
L 120 121 0 TEXT "Labels" | 181137,195652 1 0 0 "prcTxByteCtrl"
|
I 119 0 130 Builtin InPort | 155985,190696 "" ""
|
I 119 0 130 Builtin InPort | 175137,191032 "" ""
|
L 118 119 0 TEXT "Labels" | 161985,190696 1 0 0 "prcTxByteData[1:0]"
|
L 118 119 0 TEXT "Labels" | 181137,191032 1 0 0 "prcTxByteData[1:0]"
|
I 117 0 2 Builtin InPort | 156447,171985 "" ""
|
I 117 0 2 Builtin InPort | 140655,173329 "" ""
|
L 116 117 0 TEXT "Labels" | 162447,171985 1 0 0 "SIETxWEn"
|
L 116 117 0 TEXT "Labels" | 146655,173329 1 0 0 "SIETxWEn"
|
I 115 0 2 Builtin InPort | 156447,167596 "" ""
|
I 115 0 2 Builtin InPort | 140655,168940 "" ""
|
L 114 115 0 TEXT "Labels" | 162447,167596 1 0 0 "SIETxCtrl"
|
L 114 115 0 TEXT "Labels" | 146655,168940 1 0 0 "SIETxCtrl"
|
I 113 0 130 Builtin InPort | 156447,162745 "" ""
|
I 113 0 130 Builtin InPort | 140655,164089 "" ""
|
L 112 113 0 TEXT "Labels" | 162447,162745 1 0 0 "SIETxData[1:0]"
|
L 112 113 0 TEXT "Labels" | 146655,164089 1 0 0 "SIETxData[1:0]"
|
|
L 128 129 0 TEXT "Labels" | 146868,178208 1 0 0 "SIETxFSRate"
|
|
I 129 0 2 Builtin InPort | 140868,178208 "" ""
|
|
L 130 131 0 TEXT "Labels" | 181140,205088 1 0 0 "prcTxByteFSRate"
|
|
I 131 0 2 Builtin InPort | 175140,205088 "" ""
|
|
L 132 133 0 TEXT "Labels" | 148212,207440 1 0 0 "TxFSRate"
|
|
I 133 0 2 Builtin OutPort | 142212,207440 "" ""
|
END
|
END
|
