| Line 1... |
Line 1... |
VERSION=1.19
|
VERSION=1.15
|
HEADER
|
HEADER
|
FILE="usbTxWireArbiter.asf"
|
FILE="usbTxWireArbiter.asf"
|
FID=4053e959
|
FID=4053e959
|
LANGUAGE=VERILOG
|
LANGUAGE=VERILOG
|
ENTITY="USBWireTxArbiter"
|
ENTITY="USBWireTxArbiter"
|
|
FRAMES=ON
|
FREEOID=128
|
FREEOID=128
|
"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
|
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// usbTxWireArbiter\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: usbTxWireArbiter.asf,v 1.2 2004-12-18 14:36:16 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
|
MULTIPLEARCHSTATUS=FALSE
|
|
SYNTHESISATTRIBUTES=TRUE
|
|
HEADER_PARAM="AUTHOR,"
|
|
HEADER_PARAM="COMPANY,"
|
|
HEADER_PARAM="CREATIONDATE,"
|
|
HEADER_PARAM="TITLE,USBWireTxArbiter"
|
|
END
|
END
|
BUNDLES
|
BUNDLES
|
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
|
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
|
B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
|
B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
|
B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
|
B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
|
B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
|
B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
|
B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
|
B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 0
|
B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
|
B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
|
B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
|
B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
|
B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
|
B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
|
B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
|
B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1 "Arial" 4
|
B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
|
B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
|
B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
|
B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
|
B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
|
B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
|
B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
|
B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
|
B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
|
B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
|
END
|
END
|
INSTHEADER 1
|
INSTHEADER 1
|
PAGE 0,0 215900,279400
|
PAGE 25400,0 215900,279400
|
MARGINS 25400,0 0,25400
|
UPPERLEFT 0,0
|
|
GRID=OFF
|
|
GRIDSIZE 5000,5000 10000,10000
|
END
|
END
|
OBJECTS
|
OBJECTS
|
S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
|
S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
|
L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
|
L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
|
S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
|
S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
|
| Line 41... |
Line 38... |
S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
|
S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
|
L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
|
L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
|
S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
|
S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
|
L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
|
L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
|
L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
|
L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
|
F 6 0 671089152 59 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
|
F 6 0 671089152 59 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
|
G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: USBWireTxArbiter"
|
G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: USBWireTxArbiter"
|
A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
|
A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
|
C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
|
C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
|
C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
|
C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
|
W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230
|
W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230
|
W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261
|
W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261
|
W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005
|
W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005
|
W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 113773,124344 123058,120571
|
W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 113773,124344 123058,120571
|
I 20 6 0 Builtin Reset | 86247,136033
|
I 20 6 0 Builtin Reset | 86247,136033
|
A 39 9 2 TEXT "Actions" | 144675,143037 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0; \nUSBWireWEn <= 1'b0;\nTxBits <= 2'b00;\nTxCtl <= `TRI_STATE;"
|
A 39 9 2 TEXT "Actions" | 149469,142310 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0;"
|
A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
|
A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
|
L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
|
L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
|
I 59 0 3 Builtin InPort | 200032,246137 "" ""
|
I 59 0 3 Builtin InPort | 200032,246137 "" ""
|
L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
|
L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
|
I 61 0 2 Builtin InPort | 199418,251681 "" ""
|
I 61 0 2 Builtin InPort | 199418,251681 "" ""
|
| Line 83... |
Line 80... |
L 106 107 0 TEXT "Labels" | 162216,186076 1 0 0 "prcTxByteReq"
|
L 106 107 0 TEXT "Labels" | 162216,186076 1 0 0 "prcTxByteReq"
|
I 105 0 2 Builtin OutPort | 154368,153274 "" ""
|
I 105 0 2 Builtin OutPort | 154368,153274 "" ""
|
L 104 105 0 TEXT "Labels" | 160368,153274 1 0 0 "SIETxGnt"
|
L 104 105 0 TEXT "Labels" | 160368,153274 1 0 0 "SIETxGnt"
|
I 103 0 2 Builtin OutPort | 142325,212440 "" ""
|
I 103 0 2 Builtin OutPort | 142325,212440 "" ""
|
L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
|
L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
|
I 101 0 2 Builtin OutPort | 142556,217291 "" ""
|
I 101 0 130 Builtin OutPort | 142556,217291 "" ""
|
L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
|
L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
|
I 99 0 2 Builtin OutPort | 142787,221911 "" ""
|
I 99 0 2 Builtin OutPort | 142787,221911 "" ""
|
L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
|
L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
|
I 127 0 2 Builtin OutPort | 141972,231298 "" ""
|
I 127 0 2 Builtin OutPort | 141972,231298 "" ""
|
L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
|
L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
|
| Line 95... |
Line 92... |
L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
|
L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
|
I 123 0 2 Builtin InPort | 155985,199705 "" ""
|
I 123 0 2 Builtin InPort | 155985,199705 "" ""
|
L 122 123 0 TEXT "Labels" | 161985,199705 1 0 0 "prcTxByteWEn"
|
L 122 123 0 TEXT "Labels" | 161985,199705 1 0 0 "prcTxByteWEn"
|
I 121 0 2 Builtin InPort | 155985,195316 "" ""
|
I 121 0 2 Builtin InPort | 155985,195316 "" ""
|
L 120 121 0 TEXT "Labels" | 161985,195316 1 0 0 "prcTxByteCtrl"
|
L 120 121 0 TEXT "Labels" | 161985,195316 1 0 0 "prcTxByteCtrl"
|
I 119 0 2 Builtin InPort | 155985,190696 "" ""
|
I 119 0 130 Builtin InPort | 155985,190696 "" ""
|
L 118 119 0 TEXT "Labels" | 161985,190696 1 0 0 "prcTxByteData[1:0]"
|
L 118 119 0 TEXT "Labels" | 161985,190696 1 0 0 "prcTxByteData[1:0]"
|
I 117 0 2 Builtin InPort | 156447,171985 "" ""
|
I 117 0 2 Builtin InPort | 156447,171985 "" ""
|
L 116 117 0 TEXT "Labels" | 162447,171985 1 0 0 "SIETxWEn"
|
L 116 117 0 TEXT "Labels" | 162447,171985 1 0 0 "SIETxWEn"
|
I 115 0 2 Builtin InPort | 156447,167596 "" ""
|
I 115 0 2 Builtin InPort | 156447,167596 "" ""
|
L 114 115 0 TEXT "Labels" | 162447,167596 1 0 0 "SIETxCtrl"
|
L 114 115 0 TEXT "Labels" | 162447,167596 1 0 0 "SIETxCtrl"
|
I 113 0 2 Builtin InPort | 156447,162745 "" ""
|
I 113 0 130 Builtin InPort | 156447,162745 "" ""
|
L 112 113 0 TEXT "Labels" | 162447,162745 1 0 0 "SIETxData[1:0]"
|
L 112 113 0 TEXT "Labels" | 162447,162745 1 0 0 "SIETxData[1:0]"
|
END
|
END
|
