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// File : ../RTL/serialInterfaceEngine/usbTxWireArbiter.v
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// Generated : 10/06/06 19:35:31
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// From : ../RTL/serialInterfaceEngine/usbTxWireArbiter.asf
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// By : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// usbTxWireArbiter
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//// usbTxWireArbiter
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
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module USBTxWireArbiter (SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn, clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst);
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input SIETxCtrl;
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input [1:0] SIETxData;
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input SIETxFSRate;
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input SIETxReq;
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input SIETxWEn;
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input USBWireRdyIn;
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input clk;
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input clk;
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input prcTxByteCtrl;
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input prcTxByteCtrl;
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input [1:0]prcTxByteData;
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input [1:0]prcTxByteData;
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input prcTxByteFSRate;
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input prcTxByteFSRate;
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input prcTxByteReq;
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input prcTxByteReq;
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input prcTxByteWEn;
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input prcTxByteWEn;
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input rst;
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input rst;
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input SIETxCtrl;
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input [1:0]SIETxData;
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input SIETxFSRate;
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input SIETxReq;
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input SIETxWEn;
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input USBWireRdyIn;
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output prcTxByteGnt;
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output SIETxGnt;
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output SIETxGnt;
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output [1:0]TxBits;
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output [1:0]TxBits;
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output TxCtl;
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output TxCtl;
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output TxFSRate;
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output TxFSRate;
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output USBWireRdyOut;
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output USBWireRdyOut;
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output USBWireWEn;
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output USBWireWEn;
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output prcTxByteGnt;
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wire clk;
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wire prcTxByteCtrl;
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wire [1:0]prcTxByteData;
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wire prcTxByteFSRate;
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reg prcTxByteGnt, next_prcTxByteGnt;
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wire prcTxByteReq;
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wire prcTxByteWEn;
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wire rst;
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wire SIETxCtrl;
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wire SIETxCtrl;
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wire [1:0]SIETxData;
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wire [1:0]SIETxData;
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wire SIETxFSRate;
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wire SIETxFSRate;
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reg SIETxGnt, next_SIETxGnt;
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reg SIETxGnt, next_SIETxGnt;
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wire SIETxReq;
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wire SIETxReq;
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reg TxCtl, next_TxCtl;
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reg TxCtl, next_TxCtl;
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reg TxFSRate, next_TxFSRate;
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reg TxFSRate, next_TxFSRate;
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wire USBWireRdyIn;
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wire USBWireRdyIn;
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reg USBWireRdyOut, next_USBWireRdyOut;
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reg USBWireRdyOut, next_USBWireRdyOut;
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reg USBWireWEn, next_USBWireWEn;
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reg USBWireWEn, next_USBWireWEn;
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wire clk;
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wire prcTxByteCtrl;
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wire [1:0] prcTxByteData;
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wire prcTxByteFSRate;
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reg prcTxByteGnt, next_prcTxByteGnt;
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wire prcTxByteReq;
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wire prcTxByteWEn;
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wire rst;
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// diagram signals declarations
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// diagram signals declarations
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reg muxSIENotPTXB, next_muxSIENotPTXB;
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reg muxSIENotPTXB, next_muxSIENotPTXB;
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// BINARY ENCODED state machine: txWireArb
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// BINARY ENCODED state machine: txWireArb
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`define START_TARB 2'b00
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`define START_TARB 2'b00
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`define TARB_WAIT_REQ 2'b01
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`define TARB_WAIT_REQ 2'b01
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`define PTXB_ACT 2'b10
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`define PTXB_ACT 2'b10
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`define SIE_TX_ACT 2'b11
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`define SIE_TX_ACT 2'b11
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reg [1:0]CurrState_txWireArb, NextState_txWireArb;
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reg [1:0] CurrState_txWireArb;
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reg [1:0] NextState_txWireArb;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// Diagram actions (continuous assignments allowed only: assign ...)
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// processTxByte/SIETransmitter mux
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// processTxByte/SIETransmitter mux
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always @(USBWireRdyIn)
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always @(USBWireRdyIn)
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begin
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begin
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USBWireRdyOut <= USBWireRdyIn;
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USBWireRdyOut <= USBWireRdyIn;
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end
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end
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TxCtl <= prcTxByteCtrl;
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TxCtl <= prcTxByteCtrl;
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TxFSRate <= prcTxByteFSRate;
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TxFSRate <= prcTxByteFSRate;
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end
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end
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end
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end
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//--------------------------------------------------------------------
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// Machine: txWireArb
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// Machine: txWireArb
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//--------------------------------------------------------------------
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or SIETxGnt or muxSIENotPTXB or CurrState_txWireArb)
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// Next State Logic (combinatorial)
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begin
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//----------------------------------
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always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or muxSIENotPTXB or SIETxGnt or CurrState_txWireArb)
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begin : txWireArb_NextState
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NextState_txWireArb <= CurrState_txWireArb;
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NextState_txWireArb <= CurrState_txWireArb;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_prcTxByteGnt <= prcTxByteGnt;
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next_prcTxByteGnt <= prcTxByteGnt;
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next_SIETxGnt <= SIETxGnt;
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next_muxSIENotPTXB <= muxSIENotPTXB;
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next_muxSIENotPTXB <= muxSIENotPTXB;
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case (CurrState_txWireArb) // synopsys parallel_case full_case
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next_SIETxGnt <= SIETxGnt;
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case (CurrState_txWireArb)
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`START_TARB:
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`START_TARB:
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begin
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NextState_txWireArb <= `TARB_WAIT_REQ;
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NextState_txWireArb <= `TARB_WAIT_REQ;
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end
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`TARB_WAIT_REQ:
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`TARB_WAIT_REQ:
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begin
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if (prcTxByteReq == 1'b1)
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if (prcTxByteReq == 1'b1)
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begin
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begin
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NextState_txWireArb <= `PTXB_ACT;
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NextState_txWireArb <= `PTXB_ACT;
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next_prcTxByteGnt <= 1'b1;
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next_prcTxByteGnt <= 1'b1;
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next_muxSIENotPTXB <= 1'b0;
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next_muxSIENotPTXB <= 1'b0;
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begin
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begin
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NextState_txWireArb <= `SIE_TX_ACT;
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NextState_txWireArb <= `SIE_TX_ACT;
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next_SIETxGnt <= 1'b1;
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next_SIETxGnt <= 1'b1;
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next_muxSIENotPTXB <= 1'b1;
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next_muxSIENotPTXB <= 1'b1;
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end
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end
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end
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`PTXB_ACT:
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`PTXB_ACT:
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begin
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if (prcTxByteReq == 1'b0)
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if (prcTxByteReq == 1'b0)
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begin
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begin
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NextState_txWireArb <= `TARB_WAIT_REQ;
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NextState_txWireArb <= `TARB_WAIT_REQ;
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next_prcTxByteGnt <= 1'b0;
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next_prcTxByteGnt <= 1'b0;
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end
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end
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end
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`SIE_TX_ACT:
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`SIE_TX_ACT:
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begin
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if (SIETxReq == 1'b0)
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if (SIETxReq == 1'b0)
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begin
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begin
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NextState_txWireArb <= `TARB_WAIT_REQ;
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NextState_txWireArb <= `TARB_WAIT_REQ;
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next_SIETxGnt <= 1'b0;
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next_SIETxGnt <= 1'b0;
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end
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end
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end
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endcase
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endcase
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end
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end
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//----------------------------------
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin : txWireArb_CurrentState
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if (rst)
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if (rst)
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CurrState_txWireArb <= `START_TARB;
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CurrState_txWireArb <= `START_TARB;
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else
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else
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CurrState_txWireArb <= NextState_txWireArb;
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CurrState_txWireArb <= NextState_txWireArb;
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end
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end
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//----------------------------------
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// Registered outputs logic
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin : txWireArb_RegOutput
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if (rst)
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if (rst)
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begin
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begin
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muxSIENotPTXB <= 1'b0;
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prcTxByteGnt <= 1'b0;
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prcTxByteGnt <= 1'b0;
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SIETxGnt <= 1'b0;
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SIETxGnt <= 1'b0;
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muxSIENotPTXB <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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muxSIENotPTXB <= next_muxSIENotPTXB;
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prcTxByteGnt <= next_prcTxByteGnt;
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prcTxByteGnt <= next_prcTxByteGnt;
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SIETxGnt <= next_SIETxGnt;
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SIETxGnt <= next_SIETxGnt;
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muxSIENotPTXB <= next_muxSIENotPTXB;
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end
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end
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end
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end
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endmodule
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endmodule
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