URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [usbTxWireArbiter.v] - Diff between revs 5 and 7

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Rev 5	Rev 7
Line 40...	Line 40...
`//// Public License along with this source; if not, download it ////`	`//// Public License along with this source; if not, download it ////`
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// $Id: usbTxWireArbiter.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $`	`// $Id: usbTxWireArbiter.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
`//`	`//`
Line 52...	Line 52...
`include "usbConstants_h.v"	`include "usbConstants_h.v"
`include "usbSerialInterfaceEngine_h.v"	`include "usbSerialInterfaceEngine_h.v"



`module USBWireTxArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, USBWireRdyIn, USBWireRdyOut, USBWireWEn);`	`module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, USBWireRdyIn, USBWireRdyOut, USBWireWEn);`
`input clk;`	`input clk;`
`input prcTxByteCtrl;`	`input prcTxByteCtrl;`
`input [1:0]prcTxByteData;`	`input [1:0]prcTxByteData;`
`input prcTxByteReq;`	`input prcTxByteReq;`
`input prcTxByteWEn;`	`input prcTxByteWEn;`

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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [usbTxWireArbiter.v] - Diff between revs 5 and 7