| Line 83... |
Line 83... |
wire fullSpeedRate;
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wire fullSpeedRate;
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wire rst;
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wire rst;
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reg TxWireActiveDrive;
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reg TxWireActiveDrive;
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// local registers
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// local registers
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reg [2:0]buffer0;
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reg [3:0]buffer0;
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reg [2:0]buffer1;
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reg [3:0]buffer1;
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reg [2:0]buffer2;
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reg [3:0]buffer2;
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reg [2:0]buffer3;
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reg [3:0]buffer3;
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reg [2:0]bufferCnt;
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reg [2:0]bufferCnt;
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reg [1:0]bufferInIndex;
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reg [1:0]bufferInIndex;
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reg [1:0]bufferOutIndex;
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reg [1:0]bufferOutIndex;
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reg decBufferCnt;
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reg decBufferCnt;
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reg [4:0]i;
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reg [4:0]i;
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reg incBufferCnt;
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reg incBufferCnt;
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reg fullSpeedTick;
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reg fullSpeedTick;
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reg lowSpeedTick;
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reg lowSpeedTick;
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reg fullSpeedRate_reg;
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// buffer in state machine state codes:
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// buffer in state machine state codes:
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`define WAIT_BUFFER_NOT_FULL 2'b00
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`define WAIT_BUFFER_NOT_FULL 2'b00
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`define WAIT_WRITE_REQ 2'b01
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`define WAIT_WRITE_REQ 2'b01
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`define CLR_INC_BUFFER_CNT 2'b10
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`define CLR_INC_BUFFER_CNT 2'b10
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| Line 131... |
Line 132... |
//buffer input state machine
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//buffer input state machine
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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if (rst == 1'b1) begin
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incBufferCnt <= 1'b0;
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incBufferCnt <= 1'b0;
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bufferInIndex <= 2'b00;
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bufferInIndex <= 2'b00;
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buffer0 <= 3'b000;
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buffer0 <= 4'b0000;
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buffer1 <= 3'b000;
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buffer1 <= 4'b0000;
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buffer2 <= 3'b000;
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buffer2 <= 4'b0000;
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buffer3 <= 3'b000;
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buffer3 <= 4'b0000;
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USBWireRdy <= 1'b0;
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USBWireRdy <= 1'b0;
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bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
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bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
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end
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end
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else begin
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else begin
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case (bufferInStMachCurrState)
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case (bufferInStMachCurrState)
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| Line 156... |
Line 157... |
begin
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begin
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incBufferCnt <= 1'b1;
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incBufferCnt <= 1'b1;
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USBWireRdy <= 1'b0;
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USBWireRdy <= 1'b0;
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bufferInIndex <= bufferInIndex + 1'b1;
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bufferInIndex <= bufferInIndex + 1'b1;
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case (bufferInIndex)
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case (bufferInIndex)
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2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
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2'b00 : buffer0 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
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2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
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2'b01 : buffer1 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
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2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
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2'b10 : buffer2 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
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2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
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2'b11 : buffer3 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
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endcase
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endcase
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bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
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bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
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end
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end
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end
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end
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`CLR_INC_BUFFER_CNT:
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`CLR_INC_BUFFER_CNT:
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| Line 215... |
Line 216... |
decBufferCnt <= 1'b0;
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decBufferCnt <= 1'b0;
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TxBitsOut <= 2'b00;
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TxBitsOut <= 2'b00;
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TxCtrlOut <= `TRI_STATE;
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TxCtrlOut <= `TRI_STATE;
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TxDataOutTick <= 1'b0;
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TxDataOutTick <= 1'b0;
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bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
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bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
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fullSpeedRate_reg <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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case (bufferOutIndex)
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2'b00: fullSpeedRate_reg <= buffer0[3];
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2'b01: fullSpeedRate_reg <= buffer1[3];
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2'b10: fullSpeedRate_reg <= buffer2[3];
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2'b11: fullSpeedRate_reg <= buffer3[3];
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endcase
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case (bufferOutStMachCurrState)
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case (bufferOutStMachCurrState)
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`WAIT_LINE_WRITE:
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`WAIT_LINE_WRITE:
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begin
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begin
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if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
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if ((fullSpeedRate_reg == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate_reg == 1'b0 && lowSpeedTick == 1'b1) )
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begin
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begin
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TxDataOutTick <= !TxDataOutTick;
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TxDataOutTick <= !TxDataOutTick;
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if (bufferCnt == 0) begin
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if (bufferCnt == 0) begin
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TxBitsOut <= 2'b00;
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TxBitsOut <= 2'b00;
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TxCtrlOut <= `TRI_STATE;
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TxCtrlOut <= `TRI_STATE;
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