| Line 92... |
Line 92... |
input [1:0] endP1NAKTransTypeReg;
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input [1:0] endP1NAKTransTypeReg;
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input [1:0] endP2TransTypeReg;
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input [1:0] endP2TransTypeReg;
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input [1:0] endP2NAKTransTypeReg;
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input [1:0] endP2NAKTransTypeReg;
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input [1:0] endP3TransTypeReg;
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input [1:0] endP3TransTypeReg;
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input [1:0] endP3NAKTransTypeReg;
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input [1:0] endP3NAKTransTypeReg;
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output [3:0] endP0ControlReg;
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output [4:0] endP0ControlReg;
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output [3:0] endP1ControlReg;
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output [4:0] endP1ControlReg;
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output [3:0] endP2ControlReg;
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output [4:0] endP2ControlReg;
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output [3:0] endP3ControlReg;
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output [4:0] endP3ControlReg;
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input [7:0] EP0StatusReg;
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input [7:0] EP0StatusReg;
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input [7:0] EP1StatusReg;
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input [7:0] EP1StatusReg;
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input [7:0] EP2StatusReg;
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input [7:0] EP2StatusReg;
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input [7:0] EP3StatusReg;
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input [7:0] EP3StatusReg;
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output [6:0] SCAddrReg;
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output [6:0] SCAddrReg;
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| Line 141... |
Line 141... |
wire [1:0] endP1NAKTransTypeReg;
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wire [1:0] endP1NAKTransTypeReg;
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wire [1:0] endP2TransTypeReg;
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wire [1:0] endP2TransTypeReg;
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wire [1:0] endP2NAKTransTypeReg;
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wire [1:0] endP2NAKTransTypeReg;
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wire [1:0] endP3TransTypeReg;
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wire [1:0] endP3TransTypeReg;
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wire [1:0] endP3NAKTransTypeReg;
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wire [1:0] endP3NAKTransTypeReg;
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reg [3:0] endP0ControlReg;
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reg [4:0] endP0ControlReg;
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reg [3:0] endP1ControlReg;
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reg [4:0] endP1ControlReg;
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reg [3:0] endP2ControlReg;
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reg [4:0] endP2ControlReg;
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reg [3:0] endP3ControlReg;
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reg [4:0] endP3ControlReg;
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wire [7:0] EP0StatusReg;
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wire [7:0] EP0StatusReg;
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wire [7:0] EP1StatusReg;
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wire [7:0] EP1StatusReg;
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wire [7:0] EP2StatusReg;
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wire [7:0] EP2StatusReg;
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wire [7:0] EP3StatusReg;
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wire [7:0] EP3StatusReg;
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reg [6:0] SCAddrReg;
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reg [6:0] SCAddrReg;
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| Line 191... |
Line 191... |
reg EP3SetReady;
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reg EP3SetReady;
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reg EP0SendStall;
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reg EP0SendStall;
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reg EP1SendStall;
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reg EP1SendStall;
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reg EP2SendStall;
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reg EP2SendStall;
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reg EP3SendStall;
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reg EP3SendStall;
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reg EP0IsoEn;
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reg EP1IsoEn;
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reg EP2IsoEn;
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reg EP3IsoEn;
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reg EP0DataSequence;
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reg EP0DataSequence;
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reg EP1DataSequence;
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reg EP1DataSequence;
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reg EP2DataSequence;
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reg EP2DataSequence;
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reg EP3DataSequence;
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reg EP3DataSequence;
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reg EP0Enable;
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reg EP0Enable;
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| Line 208... |
Line 212... |
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//sync write demux
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//sync write demux
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (rst == 1'b1) begin
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EP0IsoEn <= 1'b0;
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EP0SendStall <= 1'b0;
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EP0DataSequence <= 1'b0;
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EP0Enable <= 1'b0;
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EP1IsoEn <= 1'b0;
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EP1SendStall <= 1'b0;
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EP1DataSequence <= 1'b0;
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EP1Enable <= 1'b0;
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EP2IsoEn <= 1'b0;
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EP2SendStall <= 1'b0;
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EP2DataSequence <= 1'b0;
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EP2Enable <= 1'b0;
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EP3IsoEn <= 1'b0;
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EP3SendStall <= 1'b0;
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EP3DataSequence <= 1'b0;
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EP3Enable <= 1'b0;
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SCControlReg <= 6'h00;
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SCAddrReg <= 7'h00;
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interruptMaskReg <= 5'h00;
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end
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else begin
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clrNAKReq <= 1'b0;
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clrNAKReq <= 1'b0;
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clrSOFReq <= 1'b0;
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clrSOFReq <= 1'b0;
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clrResetReq <= 1'b0;
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clrResetReq <= 1'b0;
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clrResInReq <= 1'b0;
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clrResInReq <= 1'b0;
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clrTransDoneReq <= 1'b0;
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clrTransDoneReq <= 1'b0;
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| Line 221... |
Line 247... |
EP3SetReady <= 1'b0;
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EP3SetReady <= 1'b0;
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if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
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if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
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begin
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begin
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case (address)
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case (address)
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`EP0_CTRL_REG : begin
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`EP0_CTRL_REG : begin
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EP0SendStall <= dataIn[3];
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EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
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EP0DataSequence <= dataIn[2];
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EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
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EP0SetReady <= dataIn[1];
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EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
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EP0Enable <= dataIn[0];
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EP0SetReady <= dataIn[`ENDPOINT_READY_BIT];
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EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
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end
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end
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`EP1_CTRL_REG : begin
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`EP1_CTRL_REG : begin
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EP1SendStall <= dataIn[3];
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EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
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EP1DataSequence <= dataIn[2];
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EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
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EP1SetReady <= dataIn[1];
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EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
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EP1Enable <= dataIn[0];
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EP1SetReady <= dataIn[`ENDPOINT_READY_BIT];
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EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
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end
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end
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`EP2_CTRL_REG : begin
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`EP2_CTRL_REG : begin
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EP2SendStall <= dataIn[3];
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EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
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EP2DataSequence <= dataIn[2];
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EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
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EP2SetReady <= dataIn[1];
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EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
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EP2Enable <= dataIn[0];
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EP2SetReady <= dataIn[`ENDPOINT_READY_BIT];
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EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
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end
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end
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`EP3_CTRL_REG : begin
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`EP3_CTRL_REG : begin
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EP3SendStall <= dataIn[3];
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EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
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EP3DataSequence <= dataIn[2];
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EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
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EP3SetReady <= dataIn[1];
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EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
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EP3Enable <= dataIn[0];
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EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
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EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
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end
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end
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`SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
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`SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
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`SC_ADDRESS : SCAddrReg <= dataIn[6:0];
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`SC_ADDRESS : SCAddrReg <= dataIn[6:0];
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`SC_INTERRUPT_STATUS_REG : begin
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`SC_INTERRUPT_STATUS_REG : begin
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clrNAKReq <= dataIn[4];
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clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
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clrSOFReq <= dataIn[3];
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clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
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clrResetReq <= dataIn[2];
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clrResetReq <= dataIn[`RESET_EVENT_BIT];
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clrResInReq <= dataIn[1];
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clrResInReq <= dataIn[`RESUME_INT_BIT];
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clrTransDoneReq <= dataIn[0];
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clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
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end
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end
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`SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[4:0];
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`SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[4:0];
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endcase
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endcase
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end
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end
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end
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end
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end
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//interrupt control
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//interrupt control
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (rst == 1'b1) begin
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NAKSentInt <= 1'b0;
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SOFRxedInt <= 1'b0;
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resetEventInt <= 1'b0;
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resumeInt <= 1'b0;
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transDoneInt <= 1'b0;
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end
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else begin
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if (NAKSentIn == 1'b1)
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if (NAKSentIn == 1'b1)
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NAKSentInt <= 1'b1;
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NAKSentInt <= 1'b1;
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else if (clrNAKReq == 1'b1)
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else if (clrNAKReq == 1'b1)
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NAKSentInt <= 1'b0;
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NAKSentInt <= 1'b0;
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| Line 286... |
Line 325... |
if (transDoneIn == 1'b1)
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if (transDoneIn == 1'b1)
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transDoneInt <= 1'b1;
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transDoneInt <= 1'b1;
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else if (clrTransDoneReq == 1'b1)
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else if (clrTransDoneReq == 1'b1)
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transDoneInt <= 1'b0;
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transDoneInt <= 1'b0;
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end
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end
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end
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|
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//mask interrupts
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//mask interrupts
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always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
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always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
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transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
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transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
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resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
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resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
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| Line 299... |
Line 339... |
end
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end
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|
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//end point ready, set/clear
|
//end point ready, set/clear
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always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
|
if (rst == 1'b1) begin
|
|
EP0Ready <= 1'b0;
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EP1Ready <= 1'b0;
|
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EP2Ready <= 1'b0;
|
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EP3Ready <= 1'b0;
|
|
end
|
|
else begin
|
if (EP0SetReady == 1'b1)
|
if (EP0SetReady == 1'b1)
|
EP0Ready <= 1'b1;
|
EP0Ready <= 1'b1;
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else if (clrEP0Ready == 1'b1)
|
else if (clrEP0Ready == 1'b1)
|
EP0Ready <= 1'b0;
|
EP0Ready <= 1'b0;
|
|
|
| Line 319... |
Line 366... |
if (EP3SetReady == 1'b1)
|
if (EP3SetReady == 1'b1)
|
EP3Ready <= 1'b1;
|
EP3Ready <= 1'b1;
|
else if (clrEP3Ready == 1'b1)
|
else if (clrEP3Ready == 1'b1)
|
EP3Ready <= 1'b0;
|
EP3Ready <= 1'b0;
|
end
|
end
|
|
end
|
|
|
//break out control signals
|
//break out control signals
|
always @(SCControlReg) begin
|
always @(SCControlReg) begin
|
SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
|
SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
|
TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
|
TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
|
| Line 330... |
Line 378... |
fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
|
fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
|
fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
|
fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
|
end
|
end
|
|
|
//combine endpoint control signals
|
//combine endpoint control signals
|
always @(EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
|
always @(EP0IsoEn or EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
|
EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
|
EP1IsoEn or EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
|
EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
|
EP2IsoEn or EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
|
EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
|
EP3IsoEn or EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
|
begin
|
begin
|
endP0ControlReg <= {EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
|
endP0ControlReg <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
|
endP1ControlReg <= {EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
|
endP1ControlReg <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
|
endP2ControlReg <= {EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
|
endP2ControlReg <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
|
endP3ControlReg <= {EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
|
endP3ControlReg <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
|
end
|
end
|
|
|
|
|
// async read mux
|
// async read mux
|
always @(address or
|
always @(address or
|
