| Line 46... |
Line 46... |
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`include "usbSlaveControl_h.v"
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`include "usbSlaveControl_h.v"
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module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
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module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
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strobe_i,
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strobe_i,
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clk, rst,
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busClk,
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rstSyncToBusClk,
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usbClk,
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rstSyncToUsbClk,
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SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
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SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
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endP0TransTypeReg, endP0NAKTransTypeReg,
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endP0TransTypeReg, endP0NAKTransTypeReg,
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endP1TransTypeReg, endP1NAKTransTypeReg,
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endP1TransTypeReg, endP1NAKTransTypeReg,
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endP2TransTypeReg, endP2NAKTransTypeReg,
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endP2TransTypeReg, endP2NAKTransTypeReg,
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endP3TransTypeReg, endP3NAKTransTypeReg,
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endP3TransTypeReg, endP3NAKTransTypeReg,
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| Line 75... |
Line 78... |
);
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);
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input [4:0] address;
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input [4:0] address;
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input [7:0] dataIn;
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input [7:0] dataIn;
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input writeEn;
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input writeEn;
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input strobe_i;
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input strobe_i;
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input clk;
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input busClk;
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input rst;
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input rstSyncToBusClk;
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input usbClk;
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input rstSyncToUsbClk;
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output [7:0] dataOut;
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output [7:0] dataOut;
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output SOFRxedIntOut;
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output SOFRxedIntOut;
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output resetEventIntOut;
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output resetEventIntOut;
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output resumeIntOut;
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output resumeIntOut;
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output transDoneIntOut;
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output transDoneIntOut;
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| Line 123... |
Line 128... |
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wire [4:0] address;
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wire [4:0] address;
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wire [7:0] dataIn;
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wire [7:0] dataIn;
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wire writeEn;
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wire writeEn;
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wire strobe_i;
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wire strobe_i;
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wire clk;
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wire busClk;
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wire rst;
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wire rstSyncToBusClk;
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wire usbClk;
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wire rstSyncToUsbClk;
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reg [7:0] dataOut;
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reg [7:0] dataOut;
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reg SOFRxedIntOut;
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reg SOFRxedIntOut;
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reg resetEventIntOut;
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reg resetEventIntOut;
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reg resumeIntOut;
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reg resumeIntOut;
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| Line 208... |
Line 215... |
reg EP0Ready;
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reg EP0Ready;
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reg EP1Ready;
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reg EP1Ready;
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reg EP2Ready;
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reg EP2Ready;
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reg EP3Ready;
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reg EP3Ready;
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//clock domain crossing sync registers
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//STB = Sync To Busclk
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reg [4:0] endP0ControlRegSTB;
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reg [4:0] endP1ControlRegSTB;
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reg [4:0] endP2ControlRegSTB;
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reg [4:0] endP3ControlRegSTB;
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reg NAKSentInSTB;
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reg SOFRxedInSTB;
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reg resetEventInSTB;
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reg resumeIntInSTB;
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reg transDoneInSTB;
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reg clrEP0ReadySTB;
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reg clrEP1ReadySTB;
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reg clrEP2ReadySTB;
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reg clrEP3ReadySTB;
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reg SCGlobalEnSTB;
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reg [1:0] TxLineStateSTB;
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reg LineDirectControlEnSTB;
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reg fullSpeedPolSTB;
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reg fullSpeedRateSTB;
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reg [7:0] EP0StatusRegSTB;
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reg [7:0] EP1StatusRegSTB;
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reg [7:0] EP2StatusRegSTB;
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reg [7:0] EP3StatusRegSTB;
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reg [1:0] endP0TransTypeRegSTB;
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reg [1:0] endP0NAKTransTypeRegSTB;
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reg [1:0] endP1TransTypeRegSTB;
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reg [1:0] endP1NAKTransTypeRegSTB;
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reg [1:0] endP2TransTypeRegSTB;
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reg [1:0] endP2NAKTransTypeRegSTB;
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reg [1:0] endP3TransTypeRegSTB;
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reg [1:0] endP3NAKTransTypeRegSTB;
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reg [10:0] frameNumSTB;
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//sync write demux
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//sync write demux
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always @(posedge clk)
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always @(posedge busClk)
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begin
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begin
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if (rst == 1'b1) begin
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if (rstSyncToBusClk == 1'b1) begin
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EP0IsoEn <= 1'b0;
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EP0IsoEn <= 1'b0;
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EP0SendStall <= 1'b0;
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EP0SendStall <= 1'b0;
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EP0DataSequence <= 1'b0;
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EP0DataSequence <= 1'b0;
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EP0Enable <= 1'b0;
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EP0Enable <= 1'b0;
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EP1IsoEn <= 1'b0;
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EP1IsoEn <= 1'b0;
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| Line 290... |
Line 331... |
end
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end
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end
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end
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end
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end
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//interrupt control
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//interrupt control
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always @(posedge clk)
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always @(posedge busClk)
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begin
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begin
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if (rst == 1'b1) begin
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if (rstSyncToBusClk == 1'b1) begin
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NAKSentInt <= 1'b0;
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NAKSentInt <= 1'b0;
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SOFRxedInt <= 1'b0;
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SOFRxedInt <= 1'b0;
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resetEventInt <= 1'b0;
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resetEventInt <= 1'b0;
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resumeInt <= 1'b0;
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resumeInt <= 1'b0;
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transDoneInt <= 1'b0;
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transDoneInt <= 1'b0;
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end
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end
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else begin
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else begin
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if (NAKSentIn == 1'b1)
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if (NAKSentInSTB == 1'b1)
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NAKSentInt <= 1'b1;
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NAKSentInt <= 1'b1;
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else if (clrNAKReq == 1'b1)
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else if (clrNAKReq == 1'b1)
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NAKSentInt <= 1'b0;
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NAKSentInt <= 1'b0;
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if (SOFRxedIn == 1'b1)
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if (SOFRxedInSTB == 1'b1)
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SOFRxedInt <= 1'b1;
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SOFRxedInt <= 1'b1;
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else if (clrSOFReq == 1'b1)
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else if (clrSOFReq == 1'b1)
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SOFRxedInt <= 1'b0;
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SOFRxedInt <= 1'b0;
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if (resetEventIn == 1'b1)
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if (resetEventInSTB == 1'b1)
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resetEventInt <= 1'b1;
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resetEventInt <= 1'b1;
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else if (clrResetReq == 1'b1)
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else if (clrResetReq == 1'b1)
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resetEventInt <= 1'b0;
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resetEventInt <= 1'b0;
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if (resumeIntIn == 1'b1)
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if (resumeIntInSTB == 1'b1)
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resumeInt <= 1'b1;
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resumeInt <= 1'b1;
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else if (clrResInReq == 1'b1)
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else if (clrResInReq == 1'b1)
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resumeInt <= 1'b0;
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resumeInt <= 1'b0;
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if (transDoneIn == 1'b1)
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if (transDoneInSTB == 1'b1)
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transDoneInt <= 1'b1;
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transDoneInt <= 1'b1;
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else if (clrTransDoneReq == 1'b1)
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else if (clrTransDoneReq == 1'b1)
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transDoneInt <= 1'b0;
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transDoneInt <= 1'b0;
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end
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end
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end
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end
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| Line 337... |
Line 378... |
SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
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SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
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NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
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NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
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end
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end
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//end point ready, set/clear
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//end point ready, set/clear
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always @(posedge clk)
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//Since 'busClk' can be a higher freq than 'usbClk',
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//'EP0SetReady' etc must be delayed with respect to other control signals, thus
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//ensuring that control signals have been clocked through to 'usbClk' clock
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//domain before the ready is asserted.
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//Not sure this is required because there is at least two 'usbClk' ticks between
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//detection of 'EP0Ready' and sampling of related control signals.always @(posedge busClk)
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always @(posedge busClk)
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begin
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begin
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if (rst == 1'b1) begin
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if (rstSyncToBusClk == 1'b1) begin
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EP0Ready <= 1'b0;
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EP0Ready <= 1'b0;
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EP1Ready <= 1'b0;
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EP1Ready <= 1'b0;
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EP2Ready <= 1'b0;
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EP2Ready <= 1'b0;
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EP3Ready <= 1'b0;
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EP3Ready <= 1'b0;
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end
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end
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else begin
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else begin
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if (EP0SetReady == 1'b1)
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if (EP0SetReady == 1'b1)
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EP0Ready <= 1'b1;
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EP0Ready <= 1'b1;
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else if (clrEP0Ready == 1'b1)
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else if (clrEP0ReadySTB == 1'b1)
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EP0Ready <= 1'b0;
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EP0Ready <= 1'b0;
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if (EP1SetReady == 1'b1)
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if (EP1SetReady == 1'b1)
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EP1Ready <= 1'b1;
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EP1Ready <= 1'b1;
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else if (clrEP1Ready == 1'b1)
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else if (clrEP1ReadySTB == 1'b1)
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EP1Ready <= 1'b0;
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EP1Ready <= 1'b0;
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if (EP2SetReady == 1'b1)
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if (EP2SetReady == 1'b1)
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EP2Ready <= 1'b1;
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EP2Ready <= 1'b1;
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else if (clrEP2Ready == 1'b1)
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else if (clrEP2ReadySTB == 1'b1)
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EP2Ready <= 1'b0;
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EP2Ready <= 1'b0;
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if (EP3SetReady == 1'b1)
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if (EP3SetReady == 1'b1)
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EP3Ready <= 1'b1;
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EP3Ready <= 1'b1;
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else if (clrEP3Ready == 1'b1)
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else if (clrEP3ReadySTB == 1'b1)
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EP3Ready <= 1'b0;
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EP3Ready <= 1'b0;
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end
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end
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end
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end
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//break out control signals
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//break out control signals
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always @(SCControlReg) begin
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always @(SCControlReg) begin
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SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
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SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
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TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
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TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
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LineDirectControlEn <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
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LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
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fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
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fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
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fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
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fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
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end
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end
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//combine endpoint control signals
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//combine endpoint control signals
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always @(EP0IsoEn or EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
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always @(EP0IsoEn or EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
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EP1IsoEn or EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
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EP1IsoEn or EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
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EP2IsoEn or EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
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EP2IsoEn or EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
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EP3IsoEn or EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
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EP3IsoEn or EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
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begin
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begin
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endP0ControlReg <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
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endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
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endP1ControlReg <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
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endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
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endP2ControlReg <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
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endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
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endP3ControlReg <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
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endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
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end
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end
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// async read mux
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// async read mux
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// FIX ME
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// Not sure why 'EP0SendStall' etc are in sensitivity list. May be related to
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// some translation bug
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always @(address or
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always @(address or
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EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
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EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
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EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
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EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
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EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
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EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
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EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
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EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
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EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
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EP0StatusRegSTB or EP1StatusRegSTB or EP2StatusRegSTB or EP3StatusRegSTB or
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endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
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endP0ControlRegSTB or endP1ControlRegSTB or endP2ControlRegSTB or endP3ControlRegSTB or
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endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or
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endP0NAKTransTypeRegSTB or endP1NAKTransTypeRegSTB or endP2NAKTransTypeRegSTB or endP3NAKTransTypeRegSTB or
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endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
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endP0TransTypeRegSTB or endP1TransTypeRegSTB or endP2TransTypeRegSTB or endP3TransTypeRegSTB or
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SCControlReg or connectStateIn or
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SCControlReg or connectStateIn or
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NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
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NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
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interruptMaskReg or SCAddrReg or frameNum)
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interruptMaskReg or SCAddrReg or frameNumSTB)
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begin
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begin
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case (address)
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case (address)
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`EP0_CTRL_REG : dataOut <= endP0ControlReg;
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`EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
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`EP0_STS_REG : dataOut <= EP0StatusReg;
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`EP0_STS_REG : dataOut <= EP0StatusRegSTB;
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`EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg;
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`EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
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`EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg;
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`EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeRegSTB;
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`EP1_CTRL_REG : dataOut <= endP1ControlReg;
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`EP1_CTRL_REG : dataOut <= endP1ControlRegSTB;
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`EP1_STS_REG : dataOut <= EP1StatusReg;
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`EP1_STS_REG : dataOut <= EP1StatusRegSTB;
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`EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg;
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`EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeRegSTB;
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`EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg;
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`EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeRegSTB;
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`EP2_CTRL_REG : dataOut <= endP2ControlReg;
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`EP2_CTRL_REG : dataOut <= endP2ControlRegSTB;
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`EP2_STS_REG : dataOut <= EP2StatusReg;
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`EP2_STS_REG : dataOut <= EP2StatusRegSTB;
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`EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg;
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`EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeRegSTB;
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`EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg;
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`EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeRegSTB;
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`EP3_CTRL_REG : dataOut <= endP3ControlReg;
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`EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
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`EP3_STS_REG : dataOut <= EP3StatusReg;
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`EP3_STS_REG : dataOut <= EP3StatusRegSTB;
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`EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg;
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`EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
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`EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg;
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`EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
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`SC_CONTROL_REG : dataOut <= SCControlReg;
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`SC_CONTROL_REG : dataOut <= SCControlReg;
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`SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn};
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`SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn};
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`SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
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`SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
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`SC_INTERRUPT_MASK_REG : dataOut <= {3'b000, interruptMaskReg};
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`SC_INTERRUPT_MASK_REG : dataOut <= {3'b000, interruptMaskReg};
|
`SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
|
`SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
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`SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNum[10:8]};
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`SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
|
`SC_FRAME_NUM_LSP : dataOut <= frameNum[7:0];
|
`SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
|
default: dataOut <= 8'h00;
|
default: dataOut <= 8'h00;
|
endcase
|
endcase
|
end
|
end
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|
|
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//re-sync from busClk to usbClk.
|
|
always @(posedge usbClk) begin
|
|
endP0ControlReg <= endP0ControlRegSTB;
|
|
endP1ControlReg <= endP1ControlRegSTB;
|
|
endP2ControlReg <= endP2ControlRegSTB;
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|
endP3ControlReg <= endP3ControlRegSTB;
|
|
SCGlobalEn <= SCGlobalEnSTB;
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|
TxLineState <= TxLineStateSTB;
|
|
LineDirectControlEn <= LineDirectControlEnSTB;
|
|
fullSpeedPol <= fullSpeedPolSTB;
|
|
fullSpeedRate <= fullSpeedRateSTB;
|
|
end
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|
|
|
//re-sync from usbClk to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc are only asserted
|
|
//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
|
|
always @(posedge busClk) begin
|
|
NAKSentInSTB <= NAKSentIn;
|
|
SOFRxedInSTB <= SOFRxedIn;
|
|
resetEventInSTB <= resetEventIn;
|
|
resumeIntInSTB <= resumeIntIn;
|
|
transDoneInSTB <= transDoneIn;
|
|
clrEP0ReadySTB <= clrEP0Ready;
|
|
clrEP1ReadySTB <= clrEP1Ready;
|
|
clrEP2ReadySTB <= clrEP2Ready;
|
|
clrEP3ReadySTB <= clrEP3Ready;
|
|
EP0StatusRegSTB <= EP0StatusReg;
|
|
EP1StatusRegSTB <= EP1StatusReg;
|
|
EP2StatusRegSTB <= EP2StatusReg;
|
|
EP3StatusRegSTB <= EP3StatusReg;
|
|
endP0TransTypeRegSTB <= endP0TransTypeReg;
|
|
endP1TransTypeRegSTB <= endP1TransTypeReg;
|
|
endP2TransTypeRegSTB <= endP2TransTypeReg;
|
|
endP3TransTypeRegSTB <= endP3TransTypeReg;
|
|
endP0NAKTransTypeRegSTB <= endP0NAKTransTypeReg;
|
|
endP1NAKTransTypeRegSTB <= endP1NAKTransTypeReg;
|
|
endP2NAKTransTypeRegSTB <= endP2NAKTransTypeReg;
|
|
endP3NAKTransTypeRegSTB <= endP3NAKTransTypeReg;
|
|
frameNumSTB <= frameNum;
|
|
end
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|
|
endmodule
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endmodule
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