| Line 48... |
Line 48... |
strobe_i,
|
strobe_i,
|
busClk,
|
busClk,
|
rstSyncToBusClk,
|
rstSyncToBusClk,
|
usbClk,
|
usbClk,
|
rstSyncToUsbClk,
|
rstSyncToUsbClk,
|
SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
|
SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut, vBusDetIntOut,
|
endP0TransTypeReg, endP0NAKTransTypeReg,
|
endP0TransTypeReg, endP0NAKTransTypeReg,
|
endP1TransTypeReg, endP1NAKTransTypeReg,
|
endP1TransTypeReg, endP1NAKTransTypeReg,
|
endP2TransTypeReg, endP2NAKTransTypeReg,
|
endP2TransTypeReg, endP2NAKTransTypeReg,
|
endP3TransTypeReg, endP3NAKTransTypeReg,
|
endP3TransTypeReg, endP3NAKTransTypeReg,
|
endP0ControlReg,
|
endP0ControlReg,
|
| Line 63... |
Line 63... |
EP1StatusReg,
|
EP1StatusReg,
|
EP2StatusReg,
|
EP2StatusReg,
|
EP3StatusReg,
|
EP3StatusReg,
|
SCAddrReg, frameNum,
|
SCAddrReg, frameNum,
|
connectStateIn,
|
connectStateIn,
|
|
vBusDetectIn,
|
SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
|
SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
|
slaveControlSelect,
|
slaveControlSelect,
|
clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
|
clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
|
TxLineState,
|
TxLineState,
|
LineDirectControlEn,
|
LineDirectControlEn,
|
fullSpeedPol,
|
fullSpeedPol,
|
fullSpeedRate,
|
fullSpeedRate,
|
|
connectSlaveToHost,
|
SCGlobalEn
|
SCGlobalEn
|
);
|
);
|
input [4:0] address;
|
input [4:0] address;
|
input [7:0] dataIn;
|
input [7:0] dataIn;
|
input writeEn;
|
input writeEn;
|
| Line 86... |
Line 88... |
output SOFRxedIntOut;
|
output SOFRxedIntOut;
|
output resetEventIntOut;
|
output resetEventIntOut;
|
output resumeIntOut;
|
output resumeIntOut;
|
output transDoneIntOut;
|
output transDoneIntOut;
|
output NAKSentIntOut;
|
output NAKSentIntOut;
|
|
output vBusDetIntOut;
|
|
|
input [1:0] endP0TransTypeReg;
|
input [1:0] endP0TransTypeReg;
|
input [1:0] endP0NAKTransTypeReg;
|
input [1:0] endP0NAKTransTypeReg;
|
input [1:0] endP1TransTypeReg;
|
input [1:0] endP1TransTypeReg;
|
input [1:0] endP1NAKTransTypeReg;
|
input [1:0] endP1NAKTransTypeReg;
|
| Line 106... |
Line 109... |
input [7:0] EP2StatusReg;
|
input [7:0] EP2StatusReg;
|
input [7:0] EP3StatusReg;
|
input [7:0] EP3StatusReg;
|
output [6:0] SCAddrReg;
|
output [6:0] SCAddrReg;
|
input [10:0] frameNum;
|
input [10:0] frameNum;
|
input [1:0] connectStateIn;
|
input [1:0] connectStateIn;
|
|
input vBusDetectIn;
|
input SOFRxedIn;
|
input SOFRxedIn;
|
input resetEventIn;
|
input resetEventIn;
|
input resumeIntIn;
|
input resumeIntIn;
|
input transDoneIn;
|
input transDoneIn;
|
input NAKSentIn;
|
input NAKSentIn;
|
| Line 120... |
Line 124... |
input clrEP3Ready;
|
input clrEP3Ready;
|
output [1:0] TxLineState;
|
output [1:0] TxLineState;
|
output LineDirectControlEn;
|
output LineDirectControlEn;
|
output fullSpeedPol;
|
output fullSpeedPol;
|
output fullSpeedRate;
|
output fullSpeedRate;
|
|
output connectSlaveToHost;
|
output SCGlobalEn;
|
output SCGlobalEn;
|
|
|
wire [4:0] address;
|
wire [4:0] address;
|
wire [7:0] dataIn;
|
wire [7:0] dataIn;
|
wire writeEn;
|
wire writeEn;
|
| Line 137... |
Line 142... |
reg SOFRxedIntOut;
|
reg SOFRxedIntOut;
|
reg resetEventIntOut;
|
reg resetEventIntOut;
|
reg resumeIntOut;
|
reg resumeIntOut;
|
reg transDoneIntOut;
|
reg transDoneIntOut;
|
reg NAKSentIntOut;
|
reg NAKSentIntOut;
|
|
reg vBusDetIntOut;
|
|
|
wire [1:0] endP0TransTypeReg;
|
wire [1:0] endP0TransTypeReg;
|
wire [1:0] endP0NAKTransTypeReg;
|
wire [1:0] endP0NAKTransTypeReg;
|
wire [1:0] endP1TransTypeReg;
|
wire [1:0] endP1TransTypeReg;
|
wire [1:0] endP1NAKTransTypeReg;
|
wire [1:0] endP1NAKTransTypeReg;
|
wire [1:0] endP2TransTypeReg;
|
wire [1:0] endP2TransTypeReg;
|
wire [1:0] endP2NAKTransTypeReg;
|
wire [1:0] endP2NAKTransTypeReg;
|
wire [1:0] endP3TransTypeReg;
|
wire [1:0] endP3TransTypeReg;
|
wire [1:0] endP3NAKTransTypeReg;
|
wire [1:0] endP3NAKTransTypeReg;
|
reg [4:0] endP0ControlReg;
|
reg [4:0] endP0ControlReg;
|
|
reg [4:0] endP0ControlReg1;
|
reg [4:0] endP1ControlReg;
|
reg [4:0] endP1ControlReg;
|
|
reg [4:0] endP1ControlReg1;
|
reg [4:0] endP2ControlReg;
|
reg [4:0] endP2ControlReg;
|
|
reg [4:0] endP2ControlReg1;
|
reg [4:0] endP3ControlReg;
|
reg [4:0] endP3ControlReg;
|
|
reg [4:0] endP3ControlReg1;
|
wire [7:0] EP0StatusReg;
|
wire [7:0] EP0StatusReg;
|
wire [7:0] EP1StatusReg;
|
wire [7:0] EP1StatusReg;
|
wire [7:0] EP2StatusReg;
|
wire [7:0] EP2StatusReg;
|
wire [7:0] EP3StatusReg;
|
wire [7:0] EP3StatusReg;
|
reg [6:0] SCAddrReg;
|
reg [6:0] SCAddrReg;
|
| Line 170... |
Line 180... |
wire clrEP0Ready;
|
wire clrEP0Ready;
|
wire clrEP1Ready;
|
wire clrEP1Ready;
|
wire clrEP2Ready;
|
wire clrEP2Ready;
|
wire clrEP3Ready;
|
wire clrEP3Ready;
|
reg [1:0] TxLineState;
|
reg [1:0] TxLineState;
|
|
reg [1:0] TxLineState_reg1;
|
reg LineDirectControlEn;
|
reg LineDirectControlEn;
|
|
reg LineDirectControlEn_reg1;
|
reg fullSpeedPol;
|
reg fullSpeedPol;
|
|
reg fullSpeedPol_reg1;
|
reg fullSpeedRate;
|
reg fullSpeedRate;
|
|
reg fullSpeedRate_reg1;
|
|
reg connectSlaveToHost;
|
|
reg connectSlaveToHost_reg1;
|
reg SCGlobalEn;
|
reg SCGlobalEn;
|
|
reg SCGlobalEn_reg1;
|
|
|
//internal wire and regs
|
//internal wire and regs
|
reg [5:0] SCControlReg;
|
reg [6:0] SCControlReg;
|
|
reg clrVBusDetReq;
|
reg clrNAKReq;
|
reg clrNAKReq;
|
reg clrSOFReq;
|
reg clrSOFReq;
|
reg clrResetReq;
|
reg clrResetReq;
|
reg clrResInReq;
|
reg clrResInReq;
|
reg clrTransDoneReq;
|
reg clrTransDoneReq;
|
reg SOFRxedInt;
|
reg SOFRxedInt;
|
reg resetEventInt;
|
reg resetEventInt;
|
reg resumeInt;
|
reg resumeInt;
|
reg transDoneInt;
|
reg transDoneInt;
|
|
reg vBusDetInt;
|
reg NAKSentInt;
|
reg NAKSentInt;
|
reg [4:0] interruptMaskReg;
|
reg [5:0] interruptMaskReg;
|
reg EP0SetReady;
|
reg EP0SetReady;
|
reg EP1SetReady;
|
reg EP1SetReady;
|
reg EP2SetReady;
|
reg EP2SetReady;
|
reg EP3SetReady;
|
reg EP3SetReady;
|
reg EP0SendStall;
|
reg EP0SendStall;
|
| Line 212... |
Line 231... |
reg EP3Enable;
|
reg EP3Enable;
|
reg EP0Ready;
|
reg EP0Ready;
|
reg EP1Ready;
|
reg EP1Ready;
|
reg EP2Ready;
|
reg EP2Ready;
|
reg EP3Ready;
|
reg EP3Ready;
|
|
reg [2:0] SOFRxedInExtend;
|
|
reg [2:0] resetEventInExtend;
|
|
reg [2:0] resumeIntInExtend;
|
|
reg [2:0] transDoneInExtend;
|
|
reg [2:0] NAKSentInExtend;
|
|
reg [2:0] clrEP0ReadyExtend;
|
|
reg [2:0] clrEP1ReadyExtend;
|
|
reg [2:0] clrEP2ReadyExtend;
|
|
reg [2:0] clrEP3ReadyExtend;
|
|
|
|
|
//clock domain crossing sync registers
|
//clock domain crossing sync registers
|
//STB = Sync To Busclk
|
//STB = Sync To Busclk
|
reg [4:0] endP0ControlRegSTB;
|
reg [4:0] endP0ControlRegSTB;
|
reg [4:0] endP1ControlRegSTB;
|
reg [4:0] endP1ControlRegSTB;
|
reg [4:0] endP2ControlRegSTB;
|
reg [4:0] endP2ControlRegSTB;
|
reg [4:0] endP3ControlRegSTB;
|
reg [4:0] endP3ControlRegSTB;
|
reg NAKSentInSTB;
|
reg [2:0] NAKSentInSTB;
|
reg SOFRxedInSTB;
|
reg [2:0] SOFRxedInSTB;
|
reg resetEventInSTB;
|
reg [2:0] resetEventInSTB;
|
reg resumeIntInSTB;
|
reg [2:0] resumeIntInSTB;
|
reg transDoneInSTB;
|
reg [2:0] transDoneInSTB;
|
reg clrEP0ReadySTB;
|
reg [2:0] clrEP0ReadySTB;
|
reg clrEP1ReadySTB;
|
reg [2:0] clrEP1ReadySTB;
|
reg clrEP2ReadySTB;
|
reg [2:0] clrEP2ReadySTB;
|
reg clrEP3ReadySTB;
|
reg [2:0] clrEP3ReadySTB;
|
reg SCGlobalEnSTB;
|
reg SCGlobalEnSTB;
|
reg [1:0] TxLineStateSTB;
|
reg [1:0] TxLineStateSTB;
|
reg LineDirectControlEnSTB;
|
reg LineDirectControlEnSTB;
|
reg fullSpeedPolSTB;
|
reg fullSpeedPolSTB;
|
reg fullSpeedRateSTB;
|
reg fullSpeedRateSTB;
|
|
reg connectSlaveToHostSTB;
|
reg [7:0] EP0StatusRegSTB;
|
reg [7:0] EP0StatusRegSTB;
|
|
reg [7:0] EP0StatusRegSTB_reg1;
|
reg [7:0] EP1StatusRegSTB;
|
reg [7:0] EP1StatusRegSTB;
|
|
reg [7:0] EP1StatusRegSTB_reg1;
|
reg [7:0] EP2StatusRegSTB;
|
reg [7:0] EP2StatusRegSTB;
|
|
reg [7:0] EP2StatusRegSTB_reg1;
|
reg [7:0] EP3StatusRegSTB;
|
reg [7:0] EP3StatusRegSTB;
|
|
reg [7:0] EP3StatusRegSTB_reg1;
|
reg [1:0] endP0TransTypeRegSTB;
|
reg [1:0] endP0TransTypeRegSTB;
|
|
reg [1:0] endP0TransTypeRegSTB_reg1;
|
reg [1:0] endP0NAKTransTypeRegSTB;
|
reg [1:0] endP0NAKTransTypeRegSTB;
|
|
reg [1:0] endP0NAKTransTypeRegSTB_reg1;
|
reg [1:0] endP1TransTypeRegSTB;
|
reg [1:0] endP1TransTypeRegSTB;
|
|
reg [1:0] endP1TransTypeRegSTB_reg1;
|
reg [1:0] endP1NAKTransTypeRegSTB;
|
reg [1:0] endP1NAKTransTypeRegSTB;
|
|
reg [1:0] endP1NAKTransTypeRegSTB_reg1;
|
reg [1:0] endP2TransTypeRegSTB;
|
reg [1:0] endP2TransTypeRegSTB;
|
|
reg [1:0] endP2TransTypeRegSTB_reg1;
|
reg [1:0] endP2NAKTransTypeRegSTB;
|
reg [1:0] endP2NAKTransTypeRegSTB;
|
|
reg [1:0] endP2NAKTransTypeRegSTB_reg1;
|
reg [1:0] endP3TransTypeRegSTB;
|
reg [1:0] endP3TransTypeRegSTB;
|
|
reg [1:0] endP3TransTypeRegSTB_reg1;
|
reg [1:0] endP3NAKTransTypeRegSTB;
|
reg [1:0] endP3NAKTransTypeRegSTB;
|
|
reg [1:0] endP3NAKTransTypeRegSTB_reg1;
|
reg [10:0] frameNumSTB;
|
reg [10:0] frameNumSTB;
|
|
reg [10:0] frameNumSTB_reg1;
|
|
reg [2:0] vBusDetectInSTB;
|
|
reg [1:0] connectStateInSTB;
|
|
reg [1:0] connectStateInSTB_reg1;
|
|
|
|
|
//sync write demux
|
//sync write demux
|
always @(posedge busClk)
|
always @(posedge busClk)
|
begin
|
begin
|
| Line 268... |
Line 314... |
EP2Enable <= 1'b0;
|
EP2Enable <= 1'b0;
|
EP3IsoEn <= 1'b0;
|
EP3IsoEn <= 1'b0;
|
EP3SendStall <= 1'b0;
|
EP3SendStall <= 1'b0;
|
EP3DataSequence <= 1'b0;
|
EP3DataSequence <= 1'b0;
|
EP3Enable <= 1'b0;
|
EP3Enable <= 1'b0;
|
SCControlReg <= 6'h00;
|
SCControlReg <= 7'h00;
|
SCAddrReg <= 7'h00;
|
SCAddrReg <= 7'h00;
|
interruptMaskReg <= 5'h00;
|
interruptMaskReg <= 6'h00;
|
end
|
end
|
else begin
|
else begin
|
|
clrVBusDetReq <= 1'b0;
|
clrNAKReq <= 1'b0;
|
clrNAKReq <= 1'b0;
|
clrSOFReq <= 1'b0;
|
clrSOFReq <= 1'b0;
|
clrResetReq <= 1'b0;
|
clrResetReq <= 1'b0;
|
clrResInReq <= 1'b0;
|
clrResInReq <= 1'b0;
|
clrTransDoneReq <= 1'b0;
|
clrTransDoneReq <= 1'b0;
|
| Line 313... |
Line 360... |
EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
|
EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
|
EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
|
EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
|
EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
|
EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
|
EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
|
EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
|
end
|
end
|
`SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
|
`SC_CONTROL_REG : SCControlReg <= dataIn[6:0];
|
`SC_ADDRESS : SCAddrReg <= dataIn[6:0];
|
`SC_ADDRESS : SCAddrReg <= dataIn[6:0];
|
`SC_INTERRUPT_STATUS_REG : begin
|
`SC_INTERRUPT_STATUS_REG : begin
|
|
clrVBusDetReq <= dataIn[`VBUS_DET_INT_BIT];
|
clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
|
clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
|
clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
|
clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
|
clrResetReq <= dataIn[`RESET_EVENT_BIT];
|
clrResetReq <= dataIn[`RESET_EVENT_BIT];
|
clrResInReq <= dataIn[`RESUME_INT_BIT];
|
clrResInReq <= dataIn[`RESUME_INT_BIT];
|
clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
|
clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
|
end
|
end
|
`SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[4:0];
|
`SC_INTERRUPT_MASK_REG : interruptMaskReg <= dataIn[5:0];
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//interrupt control
|
//interrupt control
|
always @(posedge busClk)
|
always @(posedge busClk)
|
begin
|
begin
|
if (rstSyncToBusClk == 1'b1) begin
|
if (rstSyncToBusClk == 1'b1) begin
|
|
vBusDetInt <= 1'b0;
|
NAKSentInt <= 1'b0;
|
NAKSentInt <= 1'b0;
|
SOFRxedInt <= 1'b0;
|
SOFRxedInt <= 1'b0;
|
resetEventInt <= 1'b0;
|
resetEventInt <= 1'b0;
|
resumeInt <= 1'b0;
|
resumeInt <= 1'b0;
|
transDoneInt <= 1'b0;
|
transDoneInt <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
if (NAKSentInSTB == 1'b1)
|
if (vBusDetectInSTB[0] != vBusDetectInSTB[1])
|
|
vBusDetInt <= 1'b1;
|
|
else if (clrVBusDetReq == 1'b1)
|
|
vBusDetInt <= 1'b0;
|
|
|
|
if (NAKSentInSTB[1] == 1'b1 && NAKSentInSTB[0] == 1'b0)
|
NAKSentInt <= 1'b1;
|
NAKSentInt <= 1'b1;
|
else if (clrNAKReq == 1'b1)
|
else if (clrNAKReq == 1'b1)
|
NAKSentInt <= 1'b0;
|
NAKSentInt <= 1'b0;
|
|
|
if (SOFRxedInSTB == 1'b1)
|
if (SOFRxedInSTB[1] == 1'b1 && SOFRxedInSTB[0] == 1'b0)
|
SOFRxedInt <= 1'b1;
|
SOFRxedInt <= 1'b1;
|
else if (clrSOFReq == 1'b1)
|
else if (clrSOFReq == 1'b1)
|
SOFRxedInt <= 1'b0;
|
SOFRxedInt <= 1'b0;
|
|
|
if (resetEventInSTB == 1'b1)
|
if (resetEventInSTB[1] == 1'b1 && resetEventInSTB[0] == 1'b0)
|
resetEventInt <= 1'b1;
|
resetEventInt <= 1'b1;
|
else if (clrResetReq == 1'b1)
|
else if (clrResetReq == 1'b1)
|
resetEventInt <= 1'b0;
|
resetEventInt <= 1'b0;
|
|
|
if (resumeIntInSTB == 1'b1)
|
if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0)
|
resumeInt <= 1'b1;
|
resumeInt <= 1'b1;
|
else if (clrResInReq == 1'b1)
|
else if (clrResInReq == 1'b1)
|
resumeInt <= 1'b0;
|
resumeInt <= 1'b0;
|
|
|
if (transDoneInSTB == 1'b1)
|
if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0)
|
transDoneInt <= 1'b1;
|
transDoneInt <= 1'b1;
|
else if (clrTransDoneReq == 1'b1)
|
else if (clrTransDoneReq == 1'b1)
|
transDoneInt <= 1'b0;
|
transDoneInt <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//mask interrupts
|
//mask interrupts
|
always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
|
always @(*) begin
|
transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
|
transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
|
resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
|
resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
|
resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
|
resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
|
SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
|
SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
|
NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
|
NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
|
|
vBusDetIntOut <= vBusDetInt & interruptMaskReg[`VBUS_DET_INT_BIT];
|
end
|
end
|
|
|
//end point ready, set/clear
|
//end point ready, set/clear
|
//Since 'busClk' can be a higher freq than 'usbClk',
|
//Since 'busClk' can be a higher freq than 'usbClk',
|
//'EP0SetReady' etc must be delayed with respect to other control signals, thus
|
//'EP0SetReady' etc must be delayed with respect to other control signals, thus
|
//ensuring that control signals have been clocked through to 'usbClk' clock
|
//ensuring that control signals have been clocked through to 'usbClk' clock
|
//domain before the ready is asserted.
|
//domain before the ready is asserted.
|
//Not sure this is required because there is at least two 'usbClk' ticks between
|
//Not sure this is required because there is at least two 'usbClk' ticks between
|
//detection of 'EP0Ready' and sampling of related control signals.always @(posedge busClk)
|
//detection of 'EP0Ready' and sampling of related control signals.
|
always @(posedge busClk)
|
always @(posedge busClk)
|
begin
|
begin
|
if (rstSyncToBusClk == 1'b1) begin
|
if (rstSyncToBusClk == 1'b1) begin
|
EP0Ready <= 1'b0;
|
EP0Ready <= 1'b0;
|
EP1Ready <= 1'b0;
|
EP1Ready <= 1'b0;
|
| Line 393... |
Line 448... |
EP3Ready <= 1'b0;
|
EP3Ready <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
if (EP0SetReady == 1'b1)
|
if (EP0SetReady == 1'b1)
|
EP0Ready <= 1'b1;
|
EP0Ready <= 1'b1;
|
else if (clrEP0ReadySTB == 1'b1)
|
else if (clrEP0ReadySTB[1] == 1'b1 && clrEP0ReadySTB[0] == 1'b0)
|
EP0Ready <= 1'b0;
|
EP0Ready <= 1'b0;
|
|
|
if (EP1SetReady == 1'b1)
|
if (EP1SetReady == 1'b1)
|
EP1Ready <= 1'b1;
|
EP1Ready <= 1'b1;
|
else if (clrEP1ReadySTB == 1'b1)
|
else if (clrEP1ReadySTB[1] == 1'b1 && clrEP1ReadySTB[0] == 1'b0)
|
EP1Ready <= 1'b0;
|
EP1Ready <= 1'b0;
|
|
|
if (EP2SetReady == 1'b1)
|
if (EP2SetReady == 1'b1)
|
EP2Ready <= 1'b1;
|
EP2Ready <= 1'b1;
|
else if (clrEP2ReadySTB == 1'b1)
|
else if (clrEP2ReadySTB[1] == 1'b1 && clrEP2ReadySTB[0] == 1'b0)
|
EP2Ready <= 1'b0;
|
EP2Ready <= 1'b0;
|
|
|
if (EP3SetReady == 1'b1)
|
if (EP3SetReady == 1'b1)
|
EP3Ready <= 1'b1;
|
EP3Ready <= 1'b1;
|
else if (clrEP3ReadySTB == 1'b1)
|
else if (clrEP3ReadySTB[1] == 1'b1 && clrEP3ReadySTB[0] == 1'b0)
|
EP3Ready <= 1'b0;
|
EP3Ready <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
//break out control signals
|
//break out control signals
|
| Line 420... |
Line 475... |
SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
|
SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
|
TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
|
TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
|
LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
|
LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
|
fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
|
fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
|
fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
|
fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
|
|
connectSlaveToHostSTB <= SCControlReg[`SC_CONNECT_TO_HOST_BIT];
|
end
|
end
|
|
|
//combine endpoint control signals
|
//combine endpoint control signals
|
always @(EP0IsoEn or EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
|
always @(*)
|
EP1IsoEn or EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
|
|
EP2IsoEn or EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
|
|
EP3IsoEn or EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable)
|
|
begin
|
begin
|
endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
|
endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
|
endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
|
endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
|
endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
|
endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
|
endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
|
endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
|
end
|
end
|
|
|
|
|
// async read mux
|
// async read mux
|
// FIX ME
|
always @(*)
|
// Not sure why 'EP0SendStall' etc are in sensitivity list. May be related to
|
|
// some translation bug
|
|
always @(address or
|
|
EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
|
|
EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
|
|
EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
|
|
EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
|
|
EP0StatusRegSTB or EP1StatusRegSTB or EP2StatusRegSTB or EP3StatusRegSTB or
|
|
endP0ControlRegSTB or endP1ControlRegSTB or endP2ControlRegSTB or endP3ControlRegSTB or
|
|
endP0NAKTransTypeRegSTB or endP1NAKTransTypeRegSTB or endP2NAKTransTypeRegSTB or endP3NAKTransTypeRegSTB or
|
|
endP0TransTypeRegSTB or endP1TransTypeRegSTB or endP2TransTypeRegSTB or endP3TransTypeRegSTB or
|
|
SCControlReg or connectStateIn or
|
|
NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
|
|
interruptMaskReg or SCAddrReg or frameNumSTB)
|
|
begin
|
begin
|
case (address)
|
case (address)
|
`EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
|
`EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
|
`EP0_STS_REG : dataOut <= EP0StatusRegSTB;
|
`EP0_STS_REG : dataOut <= EP0StatusRegSTB;
|
`EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
|
`EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
|
| Line 470... |
Line 509... |
`EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
|
`EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
|
`EP3_STS_REG : dataOut <= EP3StatusRegSTB;
|
`EP3_STS_REG : dataOut <= EP3StatusRegSTB;
|
`EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
|
`EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
|
`EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
|
`EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
|
`SC_CONTROL_REG : dataOut <= SCControlReg;
|
`SC_CONTROL_REG : dataOut <= SCControlReg;
|
`SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn};
|
`SC_LINE_STATUS_REG : dataOut <= {5'b00000, vBusDetectInSTB[0], connectStateInSTB};
|
`SC_INTERRUPT_STATUS_REG : dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
|
`SC_INTERRUPT_STATUS_REG : dataOut <= {2'b00, vBusDetInt, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
|
`SC_INTERRUPT_MASK_REG : dataOut <= {3'b000, interruptMaskReg};
|
`SC_INTERRUPT_MASK_REG : dataOut <= {2'b00, interruptMaskReg};
|
`SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
|
`SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
|
`SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
|
`SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
|
`SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
|
`SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
|
default: dataOut <= 8'h00;
|
default: dataOut <= 8'h00;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
//Extend SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn from 1 tick
|
|
//pulses to 3 tick pulses
|
|
always @(posedge usbClk) begin
|
|
if (rstSyncToUsbClk == 1'b1) begin
|
|
SOFRxedInExtend <= 3'b000;
|
|
resetEventInExtend <= 3'b000;
|
|
resumeIntInExtend <= 3'b000;
|
|
transDoneInExtend <= 3'b000;
|
|
NAKSentInExtend <= 3'b000;
|
|
clrEP0ReadyExtend <= 3'b000;
|
|
clrEP1ReadyExtend <= 3'b000;
|
|
clrEP2ReadyExtend <= 3'b000;
|
|
clrEP3ReadyExtend <= 3'b000;
|
|
end
|
|
else begin
|
|
if (SOFRxedIn == 1'b1)
|
|
SOFRxedInExtend <= 3'b111;
|
|
else
|
|
SOFRxedInExtend <= {1'b0, SOFRxedInExtend[2:1]};
|
|
if (resetEventIn == 1'b1)
|
|
resetEventInExtend <= 3'b111;
|
|
else
|
|
resetEventInExtend <= {1'b0, resetEventInExtend[2:1]};
|
|
if (resumeIntIn == 1'b1)
|
|
resumeIntInExtend <= 3'b111;
|
|
else
|
|
resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]};
|
|
if (transDoneIn == 1'b1)
|
|
transDoneInExtend <= 3'b111;
|
|
else
|
|
transDoneInExtend <= {1'b0, transDoneInExtend[2:1]};
|
|
if (NAKSentIn == 1'b1)
|
|
NAKSentInExtend <= 3'b111;
|
|
else
|
|
NAKSentInExtend <= {1'b0, NAKSentInExtend[2:1]};
|
|
if (clrEP0Ready == 1'b1)
|
|
clrEP0ReadyExtend <= 3'b111;
|
|
else
|
|
clrEP0ReadyExtend <= {1'b0, clrEP0ReadyExtend[2:1]};
|
|
if (clrEP1Ready == 1'b1)
|
|
clrEP1ReadyExtend <= 3'b111;
|
|
else
|
|
clrEP1ReadyExtend <= {1'b0, clrEP1ReadyExtend[2:1]};
|
|
if (clrEP2Ready == 1'b1)
|
|
clrEP2ReadyExtend <= 3'b111;
|
|
else
|
|
clrEP2ReadyExtend <= {1'b0, clrEP2ReadyExtend[2:1]};
|
|
if (clrEP3Ready == 1'b1)
|
|
clrEP3ReadyExtend <= 3'b111;
|
|
else
|
|
clrEP3ReadyExtend <= {1'b0, clrEP3ReadyExtend[2:1]};
|
|
end
|
|
end
|
|
|
//re-sync from busClk to usbClk.
|
//re-sync from busClk to usbClk.
|
always @(posedge usbClk) begin
|
always @(posedge usbClk) begin
|
endP0ControlReg <= endP0ControlRegSTB;
|
if (rstSyncToUsbClk == 1'b1) begin
|
endP1ControlReg <= endP1ControlRegSTB;
|
endP0ControlReg <= {5{1'b0}};
|
endP2ControlReg <= endP2ControlRegSTB;
|
endP0ControlReg1 <= {5{1'b0}};
|
endP3ControlReg <= endP3ControlRegSTB;
|
endP1ControlReg <= {5{1'b0}};
|
SCGlobalEn <= SCGlobalEnSTB;
|
endP1ControlReg1 <= {5{1'b0}};
|
TxLineState <= TxLineStateSTB;
|
endP2ControlReg <= {5{1'b0}};
|
LineDirectControlEn <= LineDirectControlEnSTB;
|
endP2ControlReg1 <= {5{1'b0}};
|
fullSpeedPol <= fullSpeedPolSTB;
|
endP3ControlReg <= {5{1'b0}};
|
fullSpeedRate <= fullSpeedRateSTB;
|
endP3ControlReg1 <= {5{1'b0}};
|
|
SCGlobalEn <= 1'b0;
|
|
SCGlobalEn_reg1 <= 1'b0;
|
|
TxLineState <= 2'b00;
|
|
TxLineState_reg1 <= 2'b00;
|
|
LineDirectControlEn <= 1'b0;
|
|
LineDirectControlEn_reg1 <= 1'b0;
|
|
fullSpeedPol <= 1'b0;
|
|
fullSpeedPol_reg1 <= 1'b0;
|
|
fullSpeedRate <= 1'b0;
|
|
fullSpeedRate_reg1 <= 1'b0;
|
|
connectSlaveToHost <= 1'b0;
|
|
connectSlaveToHost_reg1 <= 1'b0;
|
|
end
|
|
else begin
|
|
endP0ControlReg1 <= endP0ControlRegSTB;
|
|
endP0ControlReg <= endP0ControlReg1;
|
|
endP1ControlReg1 <= endP1ControlRegSTB;
|
|
endP1ControlReg <= endP1ControlReg1;
|
|
endP2ControlReg1 <= endP2ControlRegSTB;
|
|
endP2ControlReg <= endP2ControlReg1;
|
|
endP3ControlReg1 <= endP3ControlRegSTB;
|
|
endP3ControlReg <= endP3ControlReg1;
|
|
SCGlobalEn_reg1 <= SCGlobalEnSTB;
|
|
SCGlobalEn <= SCGlobalEn_reg1;
|
|
TxLineState_reg1 <= TxLineStateSTB;
|
|
TxLineState <= TxLineState_reg1;
|
|
LineDirectControlEn_reg1 <= LineDirectControlEnSTB;
|
|
LineDirectControlEn <= LineDirectControlEn_reg1;
|
|
fullSpeedPol_reg1 <= fullSpeedPolSTB;
|
|
fullSpeedPol <= fullSpeedPol_reg1;
|
|
fullSpeedRate_reg1 <= fullSpeedRateSTB;
|
|
fullSpeedRate <= fullSpeedRate_reg1;
|
|
connectSlaveToHost_reg1 <= connectSlaveToHostSTB;
|
|
connectSlaveToHost <= connectSlaveToHost_reg1;
|
|
end
|
end
|
end
|
|
|
//re-sync from usbClk to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc are only asserted
|
//re-sync from usbClk and async inputs to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc
|
//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
|
//are only asserted for 3 usbClk ticks
|
|
//busClk freq must be greater than usbClk/3 (plus some allowance for setup and hold) freq
|
always @(posedge busClk) begin
|
always @(posedge busClk) begin
|
NAKSentInSTB <= NAKSentIn;
|
if (rstSyncToBusClk == 1'b1) begin
|
SOFRxedInSTB <= SOFRxedIn;
|
vBusDetectInSTB <= 3'b000;
|
resetEventInSTB <= resetEventIn;
|
NAKSentInSTB <= 3'b000;
|
resumeIntInSTB <= resumeIntIn;
|
SOFRxedInSTB <= 3'b000;
|
transDoneInSTB <= transDoneIn;
|
resetEventInSTB <= 3'b000;
|
clrEP0ReadySTB <= clrEP0Ready;
|
resumeIntInSTB <= 3'b000;
|
clrEP1ReadySTB <= clrEP1Ready;
|
transDoneInSTB <= 3'b000;
|
clrEP2ReadySTB <= clrEP2Ready;
|
clrEP0ReadySTB <= 3'b000;
|
clrEP3ReadySTB <= clrEP3Ready;
|
clrEP1ReadySTB <= 3'b000;
|
EP0StatusRegSTB <= EP0StatusReg;
|
clrEP2ReadySTB <= 3'b000;
|
EP1StatusRegSTB <= EP1StatusReg;
|
clrEP3ReadySTB <= 3'b000;
|
EP2StatusRegSTB <= EP2StatusReg;
|
EP0StatusRegSTB <= 8'h00;
|
EP3StatusRegSTB <= EP3StatusReg;
|
EP0StatusRegSTB_reg1 <= 8'h00;
|
endP0TransTypeRegSTB <= endP0TransTypeReg;
|
EP1StatusRegSTB <= 8'h00;
|
endP1TransTypeRegSTB <= endP1TransTypeReg;
|
EP1StatusRegSTB_reg1 <= 8'h00;
|
endP2TransTypeRegSTB <= endP2TransTypeReg;
|
EP2StatusRegSTB <= 8'h00;
|
endP3TransTypeRegSTB <= endP3TransTypeReg;
|
EP2StatusRegSTB_reg1 <= 8'h00;
|
endP0NAKTransTypeRegSTB <= endP0NAKTransTypeReg;
|
EP3StatusRegSTB <= 8'h00;
|
endP1NAKTransTypeRegSTB <= endP1NAKTransTypeReg;
|
EP3StatusRegSTB_reg1 <= 8'h00;
|
endP2NAKTransTypeRegSTB <= endP2NAKTransTypeReg;
|
endP0TransTypeRegSTB <= 2'b00;
|
endP3NAKTransTypeRegSTB <= endP3NAKTransTypeReg;
|
endP0TransTypeRegSTB_reg1 <= 2'b00;
|
frameNumSTB <= frameNum;
|
endP1TransTypeRegSTB <= 2'b00;
|
|
endP1TransTypeRegSTB_reg1 <= 2'b00;
|
|
endP2TransTypeRegSTB <= 2'b00;
|
|
endP2TransTypeRegSTB_reg1 <= 2'b00;
|
|
endP3TransTypeRegSTB <= 2'b00;
|
|
endP3TransTypeRegSTB_reg1 <= 2'b00;
|
|
endP0NAKTransTypeRegSTB <= 2'b00;
|
|
endP0NAKTransTypeRegSTB_reg1 <= 2'b00;
|
|
endP1NAKTransTypeRegSTB <= 2'b00;
|
|
endP1NAKTransTypeRegSTB_reg1 <= 2'b00;
|
|
endP2NAKTransTypeRegSTB <= 2'b00;
|
|
endP2NAKTransTypeRegSTB_reg1 <= 2'b00;
|
|
endP3NAKTransTypeRegSTB <= 2'b00;
|
|
endP3NAKTransTypeRegSTB_reg1 <= 2'b00;
|
|
frameNumSTB <= {11{1'b0}};
|
|
frameNumSTB_reg1 <= {11{1'b0}};
|
|
connectStateInSTB <= 2'b00;
|
|
connectStateInSTB_reg1 <= 2'b00;
|
end
|
end
|
|
else begin
|
|
vBusDetectInSTB <= {vBusDetectIn, vBusDetectInSTB[2:1]};
|
|
NAKSentInSTB <= {NAKSentInExtend[0], NAKSentInSTB[2:1]};
|
|
SOFRxedInSTB <= {SOFRxedInExtend[0], SOFRxedInSTB[2:1]};
|
|
resetEventInSTB <= {resetEventInExtend[0], resetEventInSTB[2:1]};
|
|
resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]};
|
|
transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]};
|
|
clrEP0ReadySTB <= {clrEP0ReadyExtend[0], clrEP0ReadySTB[2:1]};
|
|
clrEP1ReadySTB <= {clrEP1ReadyExtend[0], clrEP1ReadySTB[2:1]};
|
|
clrEP2ReadySTB <= {clrEP2ReadyExtend[0], clrEP2ReadySTB[2:1]};
|
|
clrEP3ReadySTB <= {clrEP3ReadyExtend[0], clrEP3ReadySTB[2:1]};
|
|
EP0StatusRegSTB_reg1 <= EP0StatusReg;
|
|
EP0StatusRegSTB <= EP0StatusRegSTB_reg1;
|
|
EP1StatusRegSTB_reg1 <= EP1StatusReg;
|
|
EP1StatusRegSTB <= EP1StatusRegSTB_reg1;
|
|
EP2StatusRegSTB_reg1 <= EP2StatusReg;
|
|
EP2StatusRegSTB <= EP2StatusRegSTB_reg1;
|
|
EP3StatusRegSTB_reg1 <= EP3StatusReg;
|
|
EP3StatusRegSTB <= EP3StatusRegSTB_reg1;
|
|
endP0TransTypeRegSTB_reg1 <= endP0TransTypeReg;
|
|
endP0TransTypeRegSTB <= endP0TransTypeRegSTB_reg1;
|
|
endP1TransTypeRegSTB_reg1 <= endP1TransTypeReg;
|
|
endP1TransTypeRegSTB <= endP1TransTypeRegSTB_reg1;
|
|
endP2TransTypeRegSTB_reg1 <= endP2TransTypeReg;
|
|
endP2TransTypeRegSTB <= endP2TransTypeRegSTB_reg1;
|
|
endP3TransTypeRegSTB_reg1 <= endP3TransTypeReg;
|
|
endP3TransTypeRegSTB <= endP3TransTypeRegSTB_reg1;
|
|
endP0NAKTransTypeRegSTB_reg1 <= endP0NAKTransTypeReg;
|
|
endP0NAKTransTypeRegSTB <= endP0NAKTransTypeRegSTB_reg1;
|
|
endP1NAKTransTypeRegSTB_reg1 <= endP1NAKTransTypeReg;
|
|
endP1NAKTransTypeRegSTB <= endP1NAKTransTypeRegSTB_reg1;
|
|
endP2NAKTransTypeRegSTB_reg1 <= endP2NAKTransTypeReg;
|
|
endP2NAKTransTypeRegSTB <= endP2NAKTransTypeRegSTB_reg1;
|
|
endP3NAKTransTypeRegSTB_reg1 <= endP3NAKTransTypeReg;
|
|
endP3NAKTransTypeRegSTB <= endP3NAKTransTypeRegSTB_reg1;
|
|
frameNumSTB_reg1 <= frameNum;
|
|
frameNumSTB <= frameNumSTB_reg1;
|
|
connectStateInSTB_reg1 <= connectStateIn;
|
|
connectStateInSTB <= connectStateInSTB_reg1;
|
|
end
|
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
