| Line 95... |
Line 95... |
input RxTimeOut;
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input RxTimeOut;
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input dataSequence;
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input dataSequence;
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input ACKRxed;
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input ACKRxed;
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input [1:0] transType;
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input [1:0] transType;
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input [1:0] transTypeNAK;
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input [1:0] transTypeNAK;
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output [3:0] endPControlReg;
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output [4:0] endPControlReg;
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input clrEPRdy;
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input clrEPRdy;
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input endPMuxErrorsWEn;
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input endPMuxErrorsWEn;
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input [3:0] endP0ControlReg;
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input [4:0] endP0ControlReg;
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input [3:0] endP1ControlReg;
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input [4:0] endP1ControlReg;
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input [3:0] endP2ControlReg;
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input [4:0] endP2ControlReg;
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input [3:0] endP3ControlReg;
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input [4:0] endP3ControlReg;
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output [7:0] endP0StatusReg;
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output [7:0] endP0StatusReg;
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output [7:0] endP1StatusReg;
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output [7:0] endP1StatusReg;
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output [7:0] endP2StatusReg;
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output [7:0] endP2StatusReg;
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output [7:0] endP3StatusReg;
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output [7:0] endP3StatusReg;
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output [1:0] endP0TransTypeReg;
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output [1:0] endP0TransTypeReg;
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| Line 132... |
Line 132... |
wire RxTimeOut;
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wire RxTimeOut;
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wire dataSequence;
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wire dataSequence;
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wire ACKRxed;
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wire ACKRxed;
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wire [1:0] transType;
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wire [1:0] transType;
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wire [1:0] transTypeNAK;
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wire [1:0] transTypeNAK;
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reg [3:0] endPControlReg;
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reg [4:0] endPControlReg;
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wire clrEPRdy;
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wire clrEPRdy;
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wire endPMuxErrorsWEn;
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wire endPMuxErrorsWEn;
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wire [3:0] endP0ControlReg;
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wire [4:0] endP0ControlReg;
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wire [3:0] endP1ControlReg;
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wire [4:0] endP1ControlReg;
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wire [3:0] endP2ControlReg;
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wire [4:0] endP2ControlReg;
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wire [3:0] endP3ControlReg;
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wire [4:0] endP3ControlReg;
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reg [7:0] endP0StatusReg;
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reg [7:0] endP0StatusReg;
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reg [7:0] endP1StatusReg;
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reg [7:0] endP1StatusReg;
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reg [7:0] endP2StatusReg;
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reg [7:0] endP2StatusReg;
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reg [7:0] endP3StatusReg;
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reg [7:0] endP3StatusReg;
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reg [1:0] endP0TransTypeReg;
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reg [1:0] endP0TransTypeReg;
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