| Line 1... |
Line 1... |
|
|
|
// File : ../RTL/slaveController/slaveDirectcontrol.v
|
|
// Generated : 10/06/06 19:35:33
|
|
// From : ../RTL/slaveController/slaveDirectcontrol.asf
|
|
// By : FSM2VHDL ver. 5.0.0.9
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// slaveDirectControl
|
//// slaveDirectControl
|
//// ////
|
//// ////
|
//// This file is part of the usbhostslave opencores effort.
|
//// This file is part of the usbhostslave opencores effort.
|
| Line 41... |
Line 46... |
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
//
|
//
|
`timescale 1ns / 1ps
|
`include "timescale.v"
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbSerialInterfaceEngine_h.v"
|
|
|
module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);
|
module slaveDirectControl (SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, directControlEn, directControlLineState, rst);
|
|
input SCTxPortGnt;
|
|
input SCTxPortRdy;
|
input clk;
|
input clk;
|
input directControlEn;
|
input directControlEn;
|
input [1:0]directControlLineState;
|
input [1:0]directControlLineState;
|
input rst;
|
input rst;
|
input SCTxPortGnt;
|
|
input SCTxPortRdy;
|
|
output [7:0]SCTxPortCntl;
|
output [7:0]SCTxPortCntl;
|
output [7:0]SCTxPortData;
|
output [7:0]SCTxPortData;
|
output SCTxPortReq;
|
output SCTxPortReq;
|
output SCTxPortWEn;
|
output SCTxPortWEn;
|
|
|
wire clk;
|
|
wire directControlEn;
|
|
wire [1:0]directControlLineState;
|
|
wire rst;
|
|
reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
|
reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
|
reg [7:0]SCTxPortData, next_SCTxPortData;
|
reg [7:0]SCTxPortData, next_SCTxPortData;
|
wire SCTxPortGnt;
|
wire SCTxPortGnt;
|
wire SCTxPortRdy;
|
wire SCTxPortRdy;
|
reg SCTxPortReq, next_SCTxPortReq;
|
reg SCTxPortReq, next_SCTxPortReq;
|
reg SCTxPortWEn, next_SCTxPortWEn;
|
reg SCTxPortWEn, next_SCTxPortWEn;
|
|
wire clk;
|
|
wire directControlEn;
|
|
wire [1:0] directControlLineState;
|
|
wire rst;
|
|
|
// BINARY ENCODED state machine: slvDrctCntl
|
// BINARY ENCODED state machine: slvDrctCntl
|
// State codes definitions:
|
// State codes definitions:
|
`define START_SDC 3'b000
|
`define START_SDC 3'b000
|
`define CHK_DRCT_CNTL 3'b001
|
`define CHK_DRCT_CNTL 3'b001
|
| Line 78... |
Line 83... |
`define DRCT_CNTL_WAIT_RDY 3'b100
|
`define DRCT_CNTL_WAIT_RDY 3'b100
|
`define IDLE_FIN 3'b101
|
`define IDLE_FIN 3'b101
|
`define IDLE_WAIT_GNT 3'b110
|
`define IDLE_WAIT_GNT 3'b110
|
`define IDLE_WAIT_RDY 3'b111
|
`define IDLE_WAIT_RDY 3'b111
|
|
|
reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;
|
reg [2:0] CurrState_slvDrctCntl;
|
|
reg [2:0] NextState_slvDrctCntl;
|
|
|
// Diagram actions (continuous assignments allowed only: assign ...)
|
// Diagram actions (continuous assignments allowed only: assign ...)
|
// diagram ACTION
|
|
|
|
|
// diagram ACTION
|
|
|
|
//--------------------------------------------------------------------
|
// Machine: slvDrctCntl
|
// Machine: slvDrctCntl
|
|
//--------------------------------------------------------------------
|
// NextState logic (combinatorial)
|
//----------------------------------
|
always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)
|
// Next State Logic (combinatorial)
|
begin
|
//----------------------------------
|
|
always @ (directControlLineState or directControlEn or SCTxPortGnt or SCTxPortRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or CurrState_slvDrctCntl)
|
|
begin : slvDrctCntl_NextState
|
NextState_slvDrctCntl <= CurrState_slvDrctCntl;
|
NextState_slvDrctCntl <= CurrState_slvDrctCntl;
|
// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_SCTxPortCntl <= SCTxPortCntl;
|
|
next_SCTxPortData <= SCTxPortData;
|
|
next_SCTxPortWEn <= SCTxPortWEn;
|
|
next_SCTxPortReq <= SCTxPortReq;
|
next_SCTxPortReq <= SCTxPortReq;
|
case (CurrState_slvDrctCntl) // synopsys parallel_case full_case
|
next_SCTxPortWEn <= SCTxPortWEn;
|
|
next_SCTxPortData <= SCTxPortData;
|
|
next_SCTxPortCntl <= SCTxPortCntl;
|
|
case (CurrState_slvDrctCntl)
|
`START_SDC:
|
`START_SDC:
|
begin
|
|
NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
|
NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
|
end
|
|
`CHK_DRCT_CNTL:
|
`CHK_DRCT_CNTL:
|
begin
|
|
if (directControlEn == 1'b1)
|
if (directControlEn == 1'b1)
|
begin
|
begin
|
NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
|
NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
|
next_SCTxPortReq <= 1'b1;
|
next_SCTxPortReq <= 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
|
NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
|
next_SCTxPortReq <= 1'b1;
|
next_SCTxPortReq <= 1'b1;
|
end
|
end
|
end
|
|
`DRCT_CNTL_WAIT_GNT:
|
`DRCT_CNTL_WAIT_GNT:
|
begin
|
|
if (SCTxPortGnt == 1'b1)
|
if (SCTxPortGnt == 1'b1)
|
begin
|
|
NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
|
NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
|
end
|
|
end
|
|
`DRCT_CNTL_CHK_LOOP:
|
`DRCT_CNTL_CHK_LOOP:
|
begin
|
begin
|
next_SCTxPortWEn <= 1'b0;
|
next_SCTxPortWEn <= 1'b0;
|
if (directControlEn == 1'b0)
|
if (directControlEn == 1'b0)
|
begin
|
begin
|
NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
|
NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
|
next_SCTxPortReq <= 1'b0;
|
next_SCTxPortReq <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
|
NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
|
NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
|
end
|
end
|
end
|
|
`DRCT_CNTL_WAIT_RDY:
|
`DRCT_CNTL_WAIT_RDY:
|
begin
|
|
if (SCTxPortRdy == 1'b1)
|
if (SCTxPortRdy == 1'b1)
|
begin
|
begin
|
NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
|
NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
|
next_SCTxPortWEn <= 1'b1;
|
next_SCTxPortWEn <= 1'b1;
|
next_SCTxPortData <= {6'b000000, directControlLineState};
|
next_SCTxPortData <= {6'b000000, directControlLineState};
|
next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
|
next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
|
end
|
end
|
end
|
|
`IDLE_FIN:
|
`IDLE_FIN:
|
begin
|
begin
|
next_SCTxPortWEn <= 1'b0;
|
next_SCTxPortWEn <= 1'b0;
|
next_SCTxPortReq <= 1'b0;
|
next_SCTxPortReq <= 1'b0;
|
NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
|
NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
|
end
|
end
|
`IDLE_WAIT_GNT:
|
`IDLE_WAIT_GNT:
|
begin
|
|
if (SCTxPortGnt == 1'b1)
|
if (SCTxPortGnt == 1'b1)
|
begin
|
|
NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
|
NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
|
end
|
|
end
|
|
`IDLE_WAIT_RDY:
|
`IDLE_WAIT_RDY:
|
begin
|
|
if (SCTxPortRdy == 1'b1)
|
if (SCTxPortRdy == 1'b1)
|
begin
|
begin
|
NextState_slvDrctCntl <= `IDLE_FIN;
|
NextState_slvDrctCntl <= `IDLE_FIN;
|
next_SCTxPortWEn <= 1'b1;
|
next_SCTxPortWEn <= 1'b1;
|
next_SCTxPortData <= 8'h00;
|
next_SCTxPortData <= 8'h00;
|
next_SCTxPortCntl <= `TX_IDLE;
|
next_SCTxPortCntl <= `TX_IDLE;
|
end
|
end
|
end
|
|
endcase
|
endcase
|
end
|
end
|
|
|
|
//----------------------------------
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : slvDrctCntl_CurrentState
|
if (rst)
|
if (rst)
|
CurrState_slvDrctCntl <= `START_SDC;
|
CurrState_slvDrctCntl <= `START_SDC;
|
else
|
else
|
CurrState_slvDrctCntl <= NextState_slvDrctCntl;
|
CurrState_slvDrctCntl <= NextState_slvDrctCntl;
|
end
|
end
|
|
|
|
//----------------------------------
|
// Registered outputs logic
|
// Registered outputs logic
|
|
//----------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin : slvDrctCntl_RegOutput
|
if (rst)
|
if (rst)
|
begin
|
begin
|
SCTxPortCntl <= 8'h00;
|
SCTxPortCntl <= 8'h00;
|
SCTxPortData <= 8'h00;
|
SCTxPortData <= 8'h00;
|
SCTxPortWEn <= 1'b0;
|
SCTxPortWEn <= 1'b0;
|
