| Line 3... |
Line 3... |
FILE="slaveGetpacket.asf"
|
FILE="slaveGetpacket.asf"
|
FID=406f8b6a
|
FID=406f8b6a
|
LANGUAGE=VERILOG
|
LANGUAGE=VERILOG
|
ENTITY="slaveGetPacket"
|
ENTITY="slaveGetPacket"
|
FRAMES=ON
|
FRAMES=ON
|
FREEOID=292
|
FREEOID=294
|
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveGetPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
|
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// slaveGetPacket\n//// ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/ ////\n//// ////\n//// Module Description: ////\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from http://www.opencores.org/lgpl.shtml ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
|
END
|
END
|
BUNDLES
|
BUNDLES
|
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
|
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1 "Arial" 0
|
B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
|
B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1 "Arial" 0
|
| Line 80... |
Line 80... |
L 284 285 0 TEXT "Labels" | 166910,243470 1 0 0 "endPointReady"
|
L 284 285 0 TEXT "Labels" | 166910,243470 1 0 0 "endPointReady"
|
I 285 0 2 Builtin InPort | 160910,243470 "" ""
|
I 285 0 2 Builtin InPort | 160910,243470 "" ""
|
L 286 287 0 TEXT "State Labels" | 167860,243800 1 0 0 "EP_N_RDY\n/18/"
|
L 286 287 0 TEXT "State Labels" | 167860,243800 1 0 0 "EP_N_RDY\n/18/"
|
S 287 120 94208 ELLIPSE "States" | 167860,243800 6500 6500
|
S 287 120 94208 ELLIPSE "States" | 167860,243800 6500 6500
|
A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
|
A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
|
A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
|
A 30 23 4 TEXT "Actions" | 121604,190544 1 0 0 "RXPacketRdy <= 1'b0;\nSIERxTimeOutEn <= 1'b0;"
|
C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
|
C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
|
W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
|
W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
|
W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
|
W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
|
S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
|
S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
|
L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
|
L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
|
| Line 97... |
Line 97... |
166460,145800 160440,144225 154420,142650 142660,145310\
|
166460,145800 160440,144225 154420,142650 142660,145310\
|
136360,146115 130060,146920 116620,147480 112140,147865\
|
136360,146115 130060,146920 116620,147480 112140,147865\
|
107660,148250 105485,148701 103245,149191
|
107660,148250 105485,148701 103245,149191
|
C 290 288 0 TEXT "Conditions" | 109060,253040 1 0 0 "endPointReady == 1'b0"
|
C 290 288 0 TEXT "Conditions" | 109060,253040 1 0 0 "endPointReady == 1'b0"
|
K 291 287 0 TEXT "Comments" | 165840,251410 1 0 0 "Discard data"
|
K 291 287 0 TEXT "Comments" | 165840,251410 1 0 0 "Discard data"
|
|
L 292 293 0 TEXT "Labels" | 83089,231870 1 0 0 "SIERxTimeOutEn"
|
|
I 293 0 2 Builtin OutPort | 77089,231870 "" ""
|
C 35 34 0 TEXT "Conditions" | 122487,97401 1 0 0 "RXStreamStatus == `RX_PACKET_START"
|
C 35 34 0 TEXT "Conditions" | 122487,97401 1 0 0 "RXStreamStatus == `RX_PACKET_START"
|
W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141572,86202 141370,79031
|
W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141572,86202 141370,79031
|
S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141266,72558 6500 6500
|
S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141266,72558 6500 6500
|
L 32 33 0 TEXT "State Labels" | 141266,72558 1 0 0 "PROC_PKT"
|
L 32 33 0 TEXT "State Labels" | 141266,72558 1 0 0 "PROC_PKT"
|
L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
|
L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
|
| Line 239... |
Line 241... |
I 194 0 2 Builtin InPort | 79500,237048 "" ""
|
I 194 0 2 Builtin InPort | 79500,237048 "" ""
|
L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
|
L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
|
L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
|
L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
|
I 222 0 130 Builtin Signal | 52956,259852 "" ""
|
I 222 0 130 Builtin Signal | 52956,259852 "" ""
|
L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
|
L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
|
A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
|
A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nSIERxTimeOutEn <= 1'b1;"
|
A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
|
A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;\nSIERxTimeOutEn <= 1'b0;"
|
L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
|
L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
|
I 216 0 130 Builtin Signal | 19488,226184 "" ""
|
I 216 0 130 Builtin Signal | 19488,226184 "" ""
|
I 232 0 130 Builtin OutPort | 77780,242452 "" ""
|
I 232 0 130 Builtin OutPort | 77780,242452 "" ""
|
L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
|
L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
|
I 230 0 2 Builtin OutPort | 77548,248252 "" ""
|
I 230 0 2 Builtin OutPort | 77548,248252 "" ""
|
