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//
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//
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
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module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, endPointReady, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
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input clk;
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input clk;
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input endPointReady;
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input getPacketEn;
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input getPacketEn;
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input rst;
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input rst;
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input [7:0]RXDataIn;
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input [7:0]RXDataIn;
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input RXDataValid;
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input RXDataValid;
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input RXFifoFull;
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input RXFifoFull;
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reg ACKRxed, next_ACKRxed;
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reg ACKRxed, next_ACKRxed;
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reg bitStuffError, next_bitStuffError;
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reg bitStuffError, next_bitStuffError;
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wire clk;
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wire clk;
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reg CRCError, next_CRCError;
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reg CRCError, next_CRCError;
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reg dataSequence, next_dataSequence;
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reg dataSequence, next_dataSequence;
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wire endPointReady;
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wire getPacketEn;
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wire getPacketEn;
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wire rst;
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wire rst;
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wire [7:0]RXDataIn;
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wire [7:0]RXDataIn;
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wire RXDataValid;
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wire RXDataValid;
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reg [7:0]RXFifoData, next_RXFifoData;
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reg [7:0]RXFifoData, next_RXFifoData;
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`define WAIT_PKT 5'b01101
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`define WAIT_PKT 5'b01101
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`define CHK_PKT_START 5'b01110
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`define CHK_PKT_START 5'b01110
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`define WAIT_EN 5'b01111
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`define WAIT_EN 5'b01111
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`define PKT_RDY 5'b10000
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`define PKT_RDY 5'b10000
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`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
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`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
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`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
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reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
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reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
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// Machine: slvGetPkt
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// Machine: slvGetPkt
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
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always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or endPointReady or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
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begin
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begin
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NextState_slvGetPkt <= CurrState_slvGetPkt;
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NextState_slvGetPkt <= CurrState_slvGetPkt;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_RXOverflow <= RXOverflow;
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next_RXOverflow <= RXOverflow;
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next_ACKRxed <= ACKRxed;
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next_ACKRxed <= ACKRxed;
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NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
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NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
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end
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end
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end
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end
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`PROC_PKT_DATA_LOOP_CHK_FIFO:
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`PROC_PKT_DATA_LOOP_CHK_FIFO:
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begin
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begin
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if (RXFifoFull == 1'b1)
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if (endPointReady == 1'b0)
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begin
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NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
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end
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else if (RXFifoFull == 1'b1)
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begin
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begin
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NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
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NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
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next_RXOverflow <= 1'b1;
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next_RXOverflow <= 1'b1;
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end
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end
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else
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else
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end
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end
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`PROC_PKT_DATA_LOOP_DELAY:
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`PROC_PKT_DATA_LOOP_DELAY:
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begin
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begin
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NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
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NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
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end
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end
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`PROC_PKT_DATA_LOOP_EP_N_RDY: // Discard data
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begin
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NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
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end
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endcase
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endcase
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end
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end
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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always @ (posedge clk)
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always @ (posedge clk)
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