| Line 44... |
Line 44... |
//
|
//
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbSerialInterfaceEngine_h.v"
|
`include "usbConstants_h.v"
|
`include "usbConstants_h.v"
|
|
|
module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, endPointReady, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
|
module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, endPointReady, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut, SIERxTimeOutEn);
|
input clk;
|
input clk;
|
input endPointReady;
|
input endPointReady;
|
input getPacketEn;
|
input getPacketEn;
|
input rst;
|
input rst;
|
input [7:0]RXDataIn;
|
input [7:0]RXDataIn;
|
| Line 64... |
Line 64... |
output RXFifoWEn;
|
output RXFifoWEn;
|
output RXOverflow;
|
output RXOverflow;
|
output RXPacketRdy;
|
output RXPacketRdy;
|
output [3:0]RxPID;
|
output [3:0]RxPID;
|
output RXTimeOut;
|
output RXTimeOut;
|
|
output SIERxTimeOutEn;
|
|
|
reg ACKRxed, next_ACKRxed;
|
reg ACKRxed, next_ACKRxed;
|
reg bitStuffError, next_bitStuffError;
|
reg bitStuffError, next_bitStuffError;
|
wire clk;
|
wire clk;
|
reg CRCError, next_CRCError;
|
reg CRCError, next_CRCError;
|
| Line 84... |
Line 85... |
reg RXPacketRdy, next_RXPacketRdy;
|
reg RXPacketRdy, next_RXPacketRdy;
|
reg [3:0]RxPID, next_RxPID;
|
reg [3:0]RxPID, next_RxPID;
|
wire [7:0]RXStreamStatusIn;
|
wire [7:0]RXStreamStatusIn;
|
reg RXTimeOut, next_RXTimeOut;
|
reg RXTimeOut, next_RXTimeOut;
|
wire SIERxTimeOut;
|
wire SIERxTimeOut;
|
|
reg SIERxTimeOutEn, next_SIERxTimeOutEn;
|
|
|
// diagram signals declarations
|
// diagram signals declarations
|
reg [7:0]RXByte, next_RXByte;
|
reg [7:0]RXByte, next_RXByte;
|
reg [7:0]RXByteOld, next_RXByteOld;
|
reg [7:0]RXByteOld, next_RXByteOld;
|
reg [7:0]RXByteOldest, next_RXByteOldest;
|
reg [7:0]RXByteOldest, next_RXByteOldest;
|
| Line 119... |
Line 121... |
|
|
|
|
// Machine: slvGetPkt
|
// Machine: slvGetPkt
|
|
|
// NextState logic (combinatorial)
|
// NextState logic (combinatorial)
|
always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or endPointReady or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
|
always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or endPointReady or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or SIERxTimeOutEn or CurrState_slvGetPkt)
|
begin
|
begin
|
NextState_slvGetPkt <= CurrState_slvGetPkt;
|
NextState_slvGetPkt <= CurrState_slvGetPkt;
|
// Set default values for outputs and signals
|
// Set default values for outputs and signals
|
next_RXOverflow <= RXOverflow;
|
next_RXOverflow <= RXOverflow;
|
next_ACKRxed <= ACKRxed;
|
next_ACKRxed <= ACKRxed;
|
| Line 137... |
Line 139... |
next_RXFifoWEn <= RXFifoWEn;
|
next_RXFifoWEn <= RXFifoWEn;
|
next_RXFifoData <= RXFifoData;
|
next_RXFifoData <= RXFifoData;
|
next_RXPacketRdy <= RXPacketRdy;
|
next_RXPacketRdy <= RXPacketRdy;
|
next_RXTimeOut <= RXTimeOut;
|
next_RXTimeOut <= RXTimeOut;
|
next_RxPID <= RxPID;
|
next_RxPID <= RxPID;
|
|
next_SIERxTimeOutEn <= SIERxTimeOutEn;
|
case (CurrState_slvGetPkt) // synopsys parallel_case full_case
|
case (CurrState_slvGetPkt) // synopsys parallel_case full_case
|
`START_GP:
|
`START_GP:
|
begin
|
begin
|
NextState_slvGetPkt <= `WAIT_EN;
|
NextState_slvGetPkt <= `WAIT_EN;
|
end
|
end
|
| Line 150... |
Line 153... |
next_bitStuffError <= 1'b0;
|
next_bitStuffError <= 1'b0;
|
next_RXOverflow <= 1'b0;
|
next_RXOverflow <= 1'b0;
|
next_RXTimeOut <= 1'b0;
|
next_RXTimeOut <= 1'b0;
|
next_ACKRxed <= 1'b0;
|
next_ACKRxed <= 1'b0;
|
next_dataSequence <= 1'b0;
|
next_dataSequence <= 1'b0;
|
|
next_SIERxTimeOutEn <= 1'b1;
|
if (RXDataValid == 1'b1)
|
if (RXDataValid == 1'b1)
|
begin
|
begin
|
NextState_slvGetPkt <= `CHK_PKT_START;
|
NextState_slvGetPkt <= `CHK_PKT_START;
|
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
| Line 178... |
Line 182... |
end
|
end
|
end
|
end
|
`WAIT_EN:
|
`WAIT_EN:
|
begin
|
begin
|
next_RXPacketRdy <= 1'b0;
|
next_RXPacketRdy <= 1'b0;
|
|
next_SIERxTimeOutEn <= 1'b0;
|
if (getPacketEn == 1'b1)
|
if (getPacketEn == 1'b1)
|
begin
|
begin
|
NextState_slvGetPkt <= `WAIT_PKT;
|
NextState_slvGetPkt <= `WAIT_PKT;
|
end
|
end
|
end
|
end
|
| Line 354... |
Line 359... |
RXFifoWEn <= 1'b0;
|
RXFifoWEn <= 1'b0;
|
RXFifoData <= 8'h00;
|
RXFifoData <= 8'h00;
|
RXPacketRdy <= 1'b0;
|
RXPacketRdy <= 1'b0;
|
RXTimeOut <= 1'b0;
|
RXTimeOut <= 1'b0;
|
RxPID <= 4'h0;
|
RxPID <= 4'h0;
|
|
SIERxTimeOutEn <= 1'b0;
|
RXByte <= 8'h00;
|
RXByte <= 8'h00;
|
RXStreamStatus <= 8'h00;
|
RXStreamStatus <= 8'h00;
|
RXByteOldest <= 8'h00;
|
RXByteOldest <= 8'h00;
|
RXByteOld <= 8'h00;
|
RXByteOld <= 8'h00;
|
end
|
end
|
| Line 371... |
Line 377... |
RXFifoWEn <= next_RXFifoWEn;
|
RXFifoWEn <= next_RXFifoWEn;
|
RXFifoData <= next_RXFifoData;
|
RXFifoData <= next_RXFifoData;
|
RXPacketRdy <= next_RXPacketRdy;
|
RXPacketRdy <= next_RXPacketRdy;
|
RXTimeOut <= next_RXTimeOut;
|
RXTimeOut <= next_RXTimeOut;
|
RxPID <= next_RxPID;
|
RxPID <= next_RxPID;
|
|
SIERxTimeOutEn <= next_SIERxTimeOutEn;
|
RXByte <= next_RXByte;
|
RXByte <= next_RXByte;
|
RXStreamStatus <= next_RXStreamStatus;
|
RXStreamStatus <= next_RXStreamStatus;
|
RXByteOldest <= next_RXByteOldest;
|
RXByteOldest <= next_RXByteOldest;
|
RXByteOld <= next_RXByteOld;
|
RXByteOld <= next_RXByteOld;
|
end
|
end
|
