| Line 1... |
Line 1... |
//--------------------------------------------------------------------------------------------------
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//
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//////////////////////////////////////////////////////////////////////
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// Title : No Title
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//// ////
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// Design : usbhostslave
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//// slaveGetPacket
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// Author : Steve
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//// ////
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// Company : Base2Designs
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//// This file is part of the usbhostslave opencores effort.
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//
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//// http://www.opencores.org/cores/usbhostslave/ ////
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//-------------------------------------------------------------------------------------------------
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// File : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slaveGetpacket.v
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// $Id: slaveGetpacket.v,v 1.2 2004-12-18 14:36:20 sfielding Exp $
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// Generated : 09/22/04 06:01:23
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// From : c:\projects\USBHostSlave\RTL\slaveController\slaveGetpacket.asf
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// By : FSM2VHDL ver. 4.0.5.2
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//
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//
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//-------------------------------------------------------------------------------------------------
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// CVS Revision History
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//
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//
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// Description :
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// $Log: not supported by cvs2svn $
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//
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//
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//-------------------------------------------------------------------------------------------------
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, bitStuffError, clk, dataSequence, getPacketEn, rst);
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module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
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input clk;
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input getPacketEn;
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input rst;
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input [7:0] RXDataIn;
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input [7:0] RXDataIn;
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input RXDataValid;
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input RXDataValid;
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input RXFifoFull;
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input RXFifoFull;
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input [7:0] RXStreamStatusIn;
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input [7:0] RXStreamStatusIn;
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input SIERxTimeOut; // Single cycle pulse
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input SIERxTimeOut; // Single cycle pulse
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input clk;
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input getPacketEn;
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input rst;
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output ACKRxed;
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output ACKRxed;
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output bitStuffError;
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output CRCError;
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output CRCError;
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output dataSequence;
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output [7:0] RXFifoData;
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output [7:0] RXFifoData;
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output RXFifoWEn;
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output RXFifoWEn;
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output RXOverflow;
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output RXOverflow;
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output RXPacketRdy;
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output RXPacketRdy;
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output RXTimeOut;
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output [3:0] RxPID;
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output [3:0] RxPID;
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output bitStuffError;
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output RXTimeOut;
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output dataSequence;
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reg ACKRxed, next_ACKRxed;
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reg ACKRxed, next_ACKRxed;
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reg bitStuffError, next_bitStuffError;
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wire clk;
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reg CRCError, next_CRCError;
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reg CRCError, next_CRCError;
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reg dataSequence, next_dataSequence;
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wire getPacketEn;
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wire rst;
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wire [7:0] RXDataIn;
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wire [7:0] RXDataIn;
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wire RXDataValid;
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wire RXDataValid;
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reg [7:0] RXFifoData, next_RXFifoData;
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reg [7:0] RXFifoData, next_RXFifoData;
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wire RXFifoFull;
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wire RXFifoFull;
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reg RXFifoWEn, next_RXFifoWEn;
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reg RXFifoWEn, next_RXFifoWEn;
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reg RXOverflow, next_RXOverflow;
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reg RXOverflow, next_RXOverflow;
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reg RXPacketRdy, next_RXPacketRdy;
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reg RXPacketRdy, next_RXPacketRdy;
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reg [3:0]RxPID, next_RxPID;
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wire [7:0] RXStreamStatusIn;
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wire [7:0] RXStreamStatusIn;
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reg RXTimeOut, next_RXTimeOut;
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reg RXTimeOut, next_RXTimeOut;
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reg [3:0] RxPID, next_RxPID;
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wire SIERxTimeOut;
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wire SIERxTimeOut;
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reg bitStuffError, next_bitStuffError;
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wire clk;
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reg dataSequence, next_dataSequence;
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wire getPacketEn;
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wire rst;
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// diagram signals declarations
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// diagram signals declarations
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reg [7:0]RXByte, next_RXByte;
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reg [7:0]RXByteOld, next_RXByteOld;
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reg [7:0]RXByteOld, next_RXByteOld;
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reg [7:0]RXByteOldest, next_RXByteOldest;
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reg [7:0]RXByteOldest, next_RXByteOldest;
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reg [7:0]RXByte, next_RXByte;
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reg [7:0]RXStreamStatus, next_RXStreamStatus;
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reg [7:0]RXStreamStatus, next_RXStreamStatus;
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// BINARY ENCODED state machine: slvGetPkt
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// BINARY ENCODED state machine: slvGetPkt
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// State codes definitions:
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// State codes definitions:
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`define PROC_PKT_CHK_PID 5'b00000
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`define PROC_PKT_CHK_PID 5'b00000
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| Line 85... |
Line 115... |
`define CHK_PKT_START 5'b01110
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`define CHK_PKT_START 5'b01110
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`define WAIT_EN 5'b01111
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`define WAIT_EN 5'b01111
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`define PKT_RDY 5'b10000
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`define PKT_RDY 5'b10000
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`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
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`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
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reg [4:0] CurrState_slvGetPkt;
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reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
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reg [4:0] NextState_slvGetPkt;
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//--------------------------------------------------------------------
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// Machine: slvGetPkt
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// Machine: slvGetPkt
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//--------------------------------------------------------------------
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//----------------------------------
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// NextState logic (combinatorial)
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// NextState logic (combinatorial)
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//----------------------------------
|
always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
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always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)
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begin
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begin : slvGetPkt_NextState
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NextState_slvGetPkt <= CurrState_slvGetPkt;
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NextState_slvGetPkt <= CurrState_slvGetPkt;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_CRCError <= CRCError;
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next_bitStuffError <= bitStuffError;
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next_RXOverflow <= RXOverflow;
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next_RXOverflow <= RXOverflow;
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next_RXTimeOut <= RXTimeOut;
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next_ACKRxed <= ACKRxed;
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next_ACKRxed <= ACKRxed;
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next_dataSequence <= dataSequence;
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next_RXByte <= RXByte;
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next_RXByte <= RXByte;
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next_RXStreamStatus <= RXStreamStatus;
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next_RXStreamStatus <= RXStreamStatus;
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next_RxPID <= RxPID;
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next_RXPacketRdy <= RXPacketRdy;
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next_RXByteOldest <= RXByteOldest;
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next_RXByteOldest <= RXByteOldest;
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next_CRCError <= CRCError;
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next_bitStuffError <= bitStuffError;
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next_dataSequence <= dataSequence;
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next_RXByteOld <= RXByteOld;
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next_RXByteOld <= RXByteOld;
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next_RXFifoWEn <= RXFifoWEn;
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next_RXFifoWEn <= RXFifoWEn;
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next_RXFifoData <= RXFifoData;
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next_RXFifoData <= RXFifoData;
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next_RXPacketRdy <= RXPacketRdy;
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next_RXTimeOut <= RXTimeOut;
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next_RxPID <= RxPID;
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case (CurrState_slvGetPkt) // synopsys parallel_case full_case
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case (CurrState_slvGetPkt) // synopsys parallel_case full_case
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`START_GP:
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`START_GP:
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begin
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NextState_slvGetPkt <= `WAIT_EN;
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NextState_slvGetPkt <= `WAIT_EN;
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end
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`WAIT_PKT:
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`WAIT_PKT:
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begin
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begin
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next_CRCError <= 1'b0;
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next_CRCError <= 1'b0;
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next_bitStuffError <= 1'b0;
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next_bitStuffError <= 1'b0;
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next_RXOverflow <= 1'b0;
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next_RXOverflow <= 1'b0;
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| Line 132... |
Line 160... |
next_RXByte <= RXDataIn;
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next_RXByte <= RXDataIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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end
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end
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end
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end
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`CHK_PKT_START:
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`CHK_PKT_START:
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begin
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if (RXStreamStatus == `RX_PACKET_START)
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if (RXStreamStatus == `RX_PACKET_START)
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begin
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begin
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NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
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NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
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next_RxPID <= RXByte[3:0];
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next_RxPID <= RXByte[3:0];
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end
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end
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else
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else
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begin
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begin
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NextState_slvGetPkt <= `PKT_RDY;
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NextState_slvGetPkt <= `PKT_RDY;
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next_RXTimeOut <= 1'b1;
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next_RXTimeOut <= 1'b1;
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end
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end
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end
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`WAIT_EN:
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`WAIT_EN:
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begin
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begin
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next_RXPacketRdy <= 1'b0;
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next_RXPacketRdy <= 1'b0;
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if (getPacketEn == 1'b1)
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if (getPacketEn == 1'b1)
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begin
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NextState_slvGetPkt <= `WAIT_PKT;
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NextState_slvGetPkt <= `WAIT_PKT;
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end
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end
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end
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`PKT_RDY:
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`PKT_RDY:
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begin
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begin
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next_RXPacketRdy <= 1'b1;
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next_RXPacketRdy <= 1'b1;
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NextState_slvGetPkt <= `WAIT_EN;
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NextState_slvGetPkt <= `WAIT_EN;
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end
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end
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`PROC_PKT_CHK_PID:
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`PROC_PKT_CHK_PID:
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begin
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if (RXByte[1:0] == `HANDSHAKE)
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if (RXByte[1:0] == `HANDSHAKE)
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begin
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NextState_slvGetPkt <= `PROC_PKT_HS;
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NextState_slvGetPkt <= `PROC_PKT_HS;
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end
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else if (RXByte[1:0] == `DATA)
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else if (RXByte[1:0] == `DATA)
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begin
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NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
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NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
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end
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else
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else
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begin
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NextState_slvGetPkt <= `PKT_RDY;
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NextState_slvGetPkt <= `PKT_RDY;
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end
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end
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`PROC_PKT_HS:
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`PROC_PKT_HS:
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begin
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if (RXDataValid == 1'b1)
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if (RXDataValid == 1'b1)
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begin
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begin
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NextState_slvGetPkt <= `PKT_RDY;
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NextState_slvGetPkt <= `PKT_RDY;
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next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
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next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
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next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
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next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
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end
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end
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end
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`PROC_PKT_DATA_W_D1:
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`PROC_PKT_DATA_W_D1:
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begin
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if (RXDataValid == 1'b1)
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if (RXDataValid == 1'b1)
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begin
|
begin
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NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
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NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
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next_RXByte <= RXDataIn;
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next_RXByte <= RXDataIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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next_RXStreamStatus <= RXStreamStatusIn;
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end
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end
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end
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`PROC_PKT_DATA_CHK_D1:
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`PROC_PKT_DATA_CHK_D1:
|
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begin
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if (RXStreamStatus == `RX_PACKET_STREAM)
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if (RXStreamStatus == `RX_PACKET_STREAM)
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begin
|
begin
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NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
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NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
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next_RXByteOldest <= RXByte;
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next_RXByteOldest <= RXByte;
|
end
|
end
|
else
|
else
|
|
begin
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NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
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NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
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end
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end
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`PROC_PKT_DATA_W_D2:
|
`PROC_PKT_DATA_W_D2:
|
|
begin
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if (RXDataValid == 1'b1)
|
if (RXDataValid == 1'b1)
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
|
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
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next_RXStreamStatus <= RXStreamStatusIn;
|
end
|
end
|
|
end
|
`PROC_PKT_DATA_FIN:
|
`PROC_PKT_DATA_FIN:
|
begin
|
begin
|
next_CRCError <= RXByte[`CRC_ERROR_BIT];
|
next_CRCError <= RXByte[`CRC_ERROR_BIT];
|
next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
|
next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
|
next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
|
next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
|
NextState_slvGetPkt <= `PKT_RDY;
|
NextState_slvGetPkt <= `PKT_RDY;
|
end
|
end
|
`PROC_PKT_DATA_CHK_D2:
|
`PROC_PKT_DATA_CHK_D2:
|
|
begin
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
|
next_RXByteOld <= RXByte;
|
next_RXByteOld <= RXByte;
|
end
|
end
|
else
|
else
|
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
|
end
|
|
end
|
`PROC_PKT_DATA_W_D3:
|
`PROC_PKT_DATA_W_D3:
|
|
begin
|
if (RXDataValid == 1'b1)
|
if (RXDataValid == 1'b1)
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
|
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
next_RXStreamStatus <= RXStreamStatusIn;
|
end
|
end
|
|
end
|
`PROC_PKT_DATA_CHK_D3:
|
`PROC_PKT_DATA_CHK_D3:
|
|
begin
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
if (RXStreamStatus == `RX_PACKET_STREAM)
|
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
|
end
|
else
|
else
|
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
|
end
|
|
end
|
`PROC_PKT_DATA_LOOP_CHK_FIFO:
|
`PROC_PKT_DATA_LOOP_CHK_FIFO:
|
|
begin
|
if (RXFifoFull == 1'b1)
|
if (RXFifoFull == 1'b1)
|
begin
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
|
next_RXOverflow <= 1'b1;
|
next_RXOverflow <= 1'b1;
|
end
|
end
|
| Line 230... |
Line 293... |
next_RXFifoWEn <= 1'b1;
|
next_RXFifoWEn <= 1'b1;
|
next_RXFifoData <= RXByteOldest;
|
next_RXFifoData <= RXByteOldest;
|
next_RXByteOldest <= RXByteOld;
|
next_RXByteOldest <= RXByteOld;
|
next_RXByteOld <= RXByte;
|
next_RXByteOld <= RXByte;
|
end
|
end
|
|
end
|
`PROC_PKT_DATA_LOOP_FIFO_FULL:
|
`PROC_PKT_DATA_LOOP_FIFO_FULL:
|
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
|
|
end
|
`PROC_PKT_DATA_LOOP_W_D:
|
`PROC_PKT_DATA_LOOP_W_D:
|
begin
|
begin
|
next_RXFifoWEn <= 1'b0;
|
next_RXFifoWEn <= 1'b0;
|
if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
|
if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
|
begin
|
begin
|
| Line 247... |
Line 313... |
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
|
next_RXByte <= RXDataIn;
|
next_RXByte <= RXDataIn;
|
end
|
end
|
end
|
end
|
`PROC_PKT_DATA_LOOP_DELAY:
|
`PROC_PKT_DATA_LOOP_DELAY:
|
|
begin
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
|
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//----------------------------------
|
|
// Current State Logic (sequential)
|
// Current State Logic (sequential)
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : slvGetPkt_CurrentState
|
begin
|
if (rst)
|
if (rst)
|
CurrState_slvGetPkt <= `START_GP;
|
CurrState_slvGetPkt <= `START_GP;
|
else
|
else
|
CurrState_slvGetPkt <= NextState_slvGetPkt;
|
CurrState_slvGetPkt <= NextState_slvGetPkt;
|
end
|
end
|
|
|
//----------------------------------
|
|
// Registered outputs logic
|
// Registered outputs logic
|
//----------------------------------
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin : slvGetPkt_RegOutput
|
begin
|
if (rst)
|
if (rst)
|
begin
|
begin
|
RXByteOld <= 8'h00;
|
|
RXByteOldest <= 8'h00;
|
|
RXByte <= 8'h00;
|
|
RXStreamStatus <= 8'h00;
|
|
RXPacketRdy <= 1'b0;
|
|
RXFifoWEn <= 1'b0;
|
|
RXFifoData <= 8'h00;
|
|
CRCError <= 1'b0;
|
|
bitStuffError <= 1'b0;
|
|
RXOverflow <= 1'b0;
|
RXOverflow <= 1'b0;
|
RXTimeOut <= 1'b0;
|
|
ACKRxed <= 1'b0;
|
ACKRxed <= 1'b0;
|
|
CRCError <= 1'b0;
|
|
bitStuffError <= 1'b0;
|
dataSequence <= 1'b0;
|
dataSequence <= 1'b0;
|
|
RXFifoWEn <= 1'b0;
|
|
RXFifoData <= 8'h00;
|
|
RXPacketRdy <= 1'b0;
|
|
RXTimeOut <= 1'b0;
|
RxPID <= 4'h0;
|
RxPID <= 4'h0;
|
|
RXByte <= 8'h00;
|
|
RXStreamStatus <= 8'h00;
|
|
RXByteOldest <= 8'h00;
|
|
RXByteOld <= 8'h00;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RXByteOld <= next_RXByteOld;
|
|
RXByteOldest <= next_RXByteOldest;
|
|
RXByte <= next_RXByte;
|
|
RXStreamStatus <= next_RXStreamStatus;
|
|
RXPacketRdy <= next_RXPacketRdy;
|
|
RXFifoWEn <= next_RXFifoWEn;
|
|
RXFifoData <= next_RXFifoData;
|
|
CRCError <= next_CRCError;
|
|
bitStuffError <= next_bitStuffError;
|
|
RXOverflow <= next_RXOverflow;
|
RXOverflow <= next_RXOverflow;
|
RXTimeOut <= next_RXTimeOut;
|
|
ACKRxed <= next_ACKRxed;
|
ACKRxed <= next_ACKRxed;
|
|
CRCError <= next_CRCError;
|
|
bitStuffError <= next_bitStuffError;
|
dataSequence <= next_dataSequence;
|
dataSequence <= next_dataSequence;
|
|
RXFifoWEn <= next_RXFifoWEn;
|
|
RXFifoData <= next_RXFifoData;
|
|
RXPacketRdy <= next_RXPacketRdy;
|
|
RXTimeOut <= next_RXTimeOut;
|
RxPID <= next_RxPID;
|
RxPID <= next_RxPID;
|
|
RXByte <= next_RXByte;
|
|
RXStreamStatus <= next_RXStreamStatus;
|
|
RXByteOldest <= next_RXByteOldest;
|
|
RXByteOld <= next_RXByteOld;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
No newline at end of file
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No newline at end of file
|
