OpenCores

Rev 7	Rev 9
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`//// Public License along with this source; if not, download it ////`	`//// Public License along with this source; if not, download it ////`
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// $Id: slaveGetpacket.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $`	`timescale 1ns / 1ps
`//`
`// CVS Revision History`
`//`
`// $Log: not supported by cvs2svn $`
`//`
`include "usbSerialInterfaceEngine_h.v"	`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"	`include "usbConstants_h.v"

`module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);`	`module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);`
`input clk;`	`input clk;`
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`// Machine: slvGetPkt`	`// Machine: slvGetPkt`

`// NextState logic (combinatorial)`	`// NextState logic (combinatorial)`
`always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)`	`always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)`
`begin`	`begin`
`NextState_slvGetPkt <= CurrState_slvGetPkt;`	`NextState_slvGetPkt <= CurrState_slvGetPkt;`
`// Set default values for outputs and signals`	`// Set default values for outputs and signals`
`next_RXOverflow <= RXOverflow;`	`next_RXOverflow <= RXOverflow;`
`next_ACKRxed <= ACKRxed;`	`next_ACKRxed <= ACKRxed;`
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`begin`	`begin`
NextState_slvGetPkt <= `CHK_PKT_START;	NextState_slvGetPkt <= `CHK_PKT_START;
`next_RXByte <= RXDataIn;`	`next_RXByte <= RXDataIn;`
`next_RXStreamStatus <= RXStreamStatusIn;`	`next_RXStreamStatus <= RXStreamStatusIn;`
`end`	`end`
	`else if (SIERxTimeOut == 1'b1)`
	`begin`
	NextState_slvGetPkt <= `PKT_RDY;
	`next_RXTimeOut <= 1'b1;`
	`end`
`end`	`end`
`CHK_PKT_START:	`CHK_PKT_START:
`begin`	`begin`
if (RXStreamStatus == `RX_PACKET_START)	if (RXStreamStatus == `RX_PACKET_START)
`begin`	`begin`

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//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// $Id: slaveGetpacket.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $

`timescale 1ns / 1ps

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

`include "usbSerialInterfaceEngine_h.v"

`include "usbSerialInterfaceEngine_h.v"

`include "usbConstants_h.v"

`include "usbConstants_h.v"

module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);

module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);

input   clk;

input   clk;

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// Machine: slvGetPkt

// Machine: slvGetPkt

// NextState logic (combinatorial)

// NextState logic (combinatorial)

always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)

always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)

begin

begin

  NextState_slvGetPkt <= CurrState_slvGetPkt;

  NextState_slvGetPkt <= CurrState_slvGetPkt;

  // Set default values for outputs and signals

  // Set default values for outputs and signals

  next_RXOverflow <= RXOverflow;

  next_RXOverflow <= RXOverflow;

  next_ACKRxed <= ACKRxed;

  next_ACKRxed <= ACKRxed;

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      begin

      begin

        NextState_slvGetPkt <= `CHK_PKT_START;

        NextState_slvGetPkt <= `CHK_PKT_START;

        next_RXByte <= RXDataIn;

        next_RXByte <= RXDataIn;

        next_RXStreamStatus <= RXStreamStatusIn;

        next_RXStreamStatus <= RXStreamStatusIn;

end

end

      else if (SIERxTimeOut == 1'b1)

      begin

        NextState_slvGetPkt <= `PKT_RDY;

        next_RXTimeOut <= 1'b1;

end

end

end

    `CHK_PKT_START:

    `CHK_PKT_START:

    begin

    begin

      if (RXStreamStatus == `RX_PACKET_START)

      if (RXStreamStatus == `RX_PACKET_START)

      begin

      begin

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