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// File : ../RTL/slaveController/slaveSendpacket.v
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// Generated : 10/06/06 19:35:33
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// From : ../RTL/slaveController/slaveSendpacket.asf
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// By : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// slaveSendPacket
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//// slaveSendPacket
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//// ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// This file is part of the usbhostslave opencores effort.
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`timescale 1ns / 1ps
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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`include "usbConstants_h.v"
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module slaveSendPacket (clk, fifoData, fifoEmpty, fifoReadEn, PID, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, sendPacketRdy, sendPacketWEn);
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module slaveSendPacket (PID, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, fifoData, fifoEmpty, fifoReadEn, rst, sendPacketRdy, sendPacketWEn);
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input [3:0] PID;
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input SCTxPortGnt;
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input SCTxPortRdy;
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input clk;
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input clk;
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input [7:0]fifoData;
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input [7:0]fifoData;
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input fifoEmpty;
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input fifoEmpty;
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input [3:0]PID;
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input rst;
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input rst;
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input SCTxPortGnt;
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input SCTxPortRdy;
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input sendPacketWEn;
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input sendPacketWEn;
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output fifoReadEn;
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output [7:0]SCTxPortCntl;
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output [7:0]SCTxPortCntl;
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output [7:0]SCTxPortData;
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output [7:0]SCTxPortData;
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output SCTxPortReq;
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output SCTxPortReq;
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output SCTxPortWEn;
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output SCTxPortWEn;
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output fifoReadEn;
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output sendPacketRdy;
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output sendPacketRdy;
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wire clk;
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wire [7:0]fifoData;
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wire fifoEmpty;
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reg fifoReadEn, next_fifoReadEn;
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wire [3:0]PID;
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wire [3:0]PID;
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wire rst;
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reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
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reg [7:0]SCTxPortCntl, next_SCTxPortCntl;
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reg [7:0]SCTxPortData, next_SCTxPortData;
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reg [7:0]SCTxPortData, next_SCTxPortData;
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wire SCTxPortGnt;
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wire SCTxPortGnt;
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wire SCTxPortRdy;
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wire SCTxPortRdy;
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reg SCTxPortReq, next_SCTxPortReq;
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reg SCTxPortReq, next_SCTxPortReq;
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reg SCTxPortWEn, next_SCTxPortWEn;
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reg SCTxPortWEn, next_SCTxPortWEn;
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wire clk;
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wire [7:0] fifoData;
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wire fifoEmpty;
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reg fifoReadEn, next_fifoReadEn;
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wire rst;
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reg sendPacketRdy, next_sendPacketRdy;
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reg sendPacketRdy, next_sendPacketRdy;
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wire sendPacketWEn;
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wire sendPacketWEn;
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// diagram signals declarations
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// diagram signals declarations
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reg [7:0]PIDNotPID;
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reg [7:0]PIDNotPID;
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`define SP_D0_D1_TERM_BYTE 4'b1010
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`define SP_D0_D1_TERM_BYTE 4'b1010
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`define SP_NOT_DATA 4'b1011
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`define SP_NOT_DATA 4'b1011
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`define SP_D0_D1_CLR_WEN 4'b1100
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`define SP_D0_D1_CLR_WEN 4'b1100
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`define SP_D0_D1_CLR_REN 4'b1101
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`define SP_D0_D1_CLR_REN 4'b1101
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reg [3:0]CurrState_slvSndPkt, NextState_slvSndPkt;
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reg [3:0] CurrState_slvSndPkt;
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reg [3:0] NextState_slvSndPkt;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// Diagram actions (continuous assignments allowed only: assign ...)
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always @(PID)
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always @(PID)
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begin
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begin
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PIDNotPID <= { (PID ^ 4'hf), PID };
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PIDNotPID <= { (PID ^ 4'hf), PID };
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end
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end
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//--------------------------------------------------------------------
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// Machine: slvSndPkt
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// Machine: slvSndPkt
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//--------------------------------------------------------------------
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// NextState logic (combinatorial)
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//----------------------------------
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always @ (sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PIDNotPID or PID or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or SCTxPortData or SCTxPortCntl or SCTxPortWEn or SCTxPortReq or CurrState_slvSndPkt)
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// Next State Logic (combinatorial)
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begin
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//----------------------------------
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always @ (PIDNotPID or fifoData or sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PID or fifoEmpty or sendPacketRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or fifoReadEn or CurrState_slvSndPkt)
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begin : slvSndPkt_NextState
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NextState_slvSndPkt <= CurrState_slvSndPkt;
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NextState_slvSndPkt <= CurrState_slvSndPkt;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_sendPacketRdy <= sendPacketRdy;
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next_sendPacketRdy <= sendPacketRdy;
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next_fifoReadEn <= fifoReadEn;
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next_SCTxPortReq <= SCTxPortReq;
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next_SCTxPortWEn <= SCTxPortWEn;
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next_SCTxPortData <= SCTxPortData;
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next_SCTxPortData <= SCTxPortData;
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next_SCTxPortCntl <= SCTxPortCntl;
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next_SCTxPortCntl <= SCTxPortCntl;
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next_SCTxPortWEn <= SCTxPortWEn;
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next_fifoReadEn <= fifoReadEn;
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next_SCTxPortReq <= SCTxPortReq;
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case (CurrState_slvSndPkt)
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case (CurrState_slvSndPkt) // synopsys parallel_case full_case
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`START_SP1:
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`START_SP1:
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begin
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NextState_slvSndPkt <= `SP_WAIT_ENABLE;
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NextState_slvSndPkt <= `SP_WAIT_ENABLE;
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end
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`SP_WAIT_ENABLE:
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`SP_WAIT_ENABLE:
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begin
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if (sendPacketWEn == 1'b1)
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if (sendPacketWEn == 1'b1)
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begin
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begin
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NextState_slvSndPkt <= `SP1_WAIT_GNT;
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NextState_slvSndPkt <= `SP1_WAIT_GNT;
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next_sendPacketRdy <= 1'b0;
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next_sendPacketRdy <= 1'b0;
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next_SCTxPortReq <= 1'b1;
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next_SCTxPortReq <= 1'b1;
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end
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end
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end
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`SP1_WAIT_GNT:
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`SP1_WAIT_GNT:
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begin
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if (SCTxPortGnt == 1'b1)
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if (SCTxPortGnt == 1'b1)
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begin
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NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
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NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
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end
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end
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`FIN_SP1:
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`FIN_SP1:
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begin
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begin
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NextState_slvSndPkt <= `SP_WAIT_ENABLE;
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NextState_slvSndPkt <= `SP_WAIT_ENABLE;
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next_sendPacketRdy <= 1'b1;
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next_sendPacketRdy <= 1'b1;
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next_SCTxPortReq <= 1'b0;
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next_SCTxPortReq <= 1'b0;
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end
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end
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`SP_NOT_DATA:
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`SP_NOT_DATA:
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begin
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NextState_slvSndPkt <= `FIN_SP1;
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NextState_slvSndPkt <= `FIN_SP1;
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end
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`SP_SEND_PID_WAIT_RDY:
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`SP_SEND_PID_WAIT_RDY:
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begin
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if (SCTxPortRdy == 1'b1)
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if (SCTxPortRdy == 1'b1)
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begin
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begin
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NextState_slvSndPkt <= `SP_SEND_PID_FIN;
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NextState_slvSndPkt <= `SP_SEND_PID_FIN;
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next_SCTxPortWEn <= 1'b1;
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next_SCTxPortWEn <= 1'b1;
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next_SCTxPortData <= PIDNotPID;
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next_SCTxPortData <= PIDNotPID;
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next_SCTxPortCntl <= `TX_PACKET_START;
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next_SCTxPortCntl <= `TX_PACKET_START;
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end
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end
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end
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`SP_SEND_PID_FIN:
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`SP_SEND_PID_FIN:
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begin
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begin
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next_SCTxPortWEn <= 1'b0;
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next_SCTxPortWEn <= 1'b0;
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if (PID == `DATA0 || PID == `DATA1)
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if (PID == `DATA0 || PID == `DATA1)
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begin
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NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
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NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
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end
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else
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else
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begin
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NextState_slvSndPkt <= `SP_NOT_DATA;
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NextState_slvSndPkt <= `SP_NOT_DATA;
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end
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end
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end
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`SP_D0_D1_READ_FIFO:
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`SP_D0_D1_READ_FIFO:
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begin
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begin
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next_SCTxPortWEn <= 1'b1;
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next_SCTxPortWEn <= 1'b1;
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next_SCTxPortData <= fifoData;
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next_SCTxPortData <= fifoData;
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next_SCTxPortCntl <= `TX_PACKET_STREAM;
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next_SCTxPortCntl <= `TX_PACKET_STREAM;
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NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
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NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
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end
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end
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`SP_D0_D1_WAIT_READ_FIFO:
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`SP_D0_D1_WAIT_READ_FIFO:
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begin
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if (SCTxPortRdy == 1'b1)
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if (SCTxPortRdy == 1'b1)
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begin
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begin
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NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
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NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
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next_fifoReadEn <= 1'b1;
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next_fifoReadEn <= 1'b1;
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end
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end
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end
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`SP_D0_D1_FIFO_EMPTY:
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`SP_D0_D1_FIFO_EMPTY:
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begin
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if (fifoEmpty == 1'b0)
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if (fifoEmpty == 1'b0)
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begin
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NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
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NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
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end
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else
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else
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begin
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NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
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NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
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end
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end
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`SP_D0_D1_FIN:
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`SP_D0_D1_FIN:
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begin
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begin
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next_SCTxPortWEn <= 1'b0;
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next_SCTxPortWEn <= 1'b0;
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NextState_slvSndPkt <= `FIN_SP1;
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NextState_slvSndPkt <= `FIN_SP1;
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end
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end
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`SP_D0_D1_TERM_BYTE:
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`SP_D0_D1_TERM_BYTE:
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begin
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if (SCTxPortRdy == 1'b1)
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if (SCTxPortRdy == 1'b1)
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begin
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begin
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NextState_slvSndPkt <= `SP_D0_D1_FIN;
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NextState_slvSndPkt <= `SP_D0_D1_FIN;
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//Last byte is not valid data,
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//Last byte is not valid data,
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//but the 'TX_PACKET_STOP' flag is required
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//but the 'TX_PACKET_STOP' flag is required
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//by the SIE state machine to detect end of data packet
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//by the SIE state machine to detect end of data packet
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next_SCTxPortWEn <= 1'b1;
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next_SCTxPortWEn <= 1'b1;
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next_SCTxPortData <= 8'h00;
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next_SCTxPortData <= 8'h00;
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next_SCTxPortCntl <= `TX_PACKET_STOP;
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next_SCTxPortCntl <= `TX_PACKET_STOP;
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end
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end
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end
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`SP_D0_D1_CLR_WEN:
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`SP_D0_D1_CLR_WEN:
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begin
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begin
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next_SCTxPortWEn <= 1'b0;
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next_SCTxPortWEn <= 1'b0;
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NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
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NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
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end
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end
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NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
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NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
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end
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end
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endcase
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endcase
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end
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end
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//----------------------------------
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin : slvSndPkt_CurrentState
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if (rst)
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if (rst)
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CurrState_slvSndPkt <= `START_SP1;
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CurrState_slvSndPkt <= `START_SP1;
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else
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else
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CurrState_slvSndPkt <= NextState_slvSndPkt;
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CurrState_slvSndPkt <= NextState_slvSndPkt;
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end
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end
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//----------------------------------
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// Registered outputs logic
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin : slvSndPkt_RegOutput
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if (rst)
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if (rst)
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begin
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begin
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sendPacketRdy <= 1'b1;
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sendPacketRdy <= 1'b1;
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fifoReadEn <= 1'b0;
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SCTxPortReq <= 1'b0;
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SCTxPortWEn <= 1'b0;
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SCTxPortData <= 8'h00;
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SCTxPortData <= 8'h00;
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SCTxPortCntl <= 8'h00;
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SCTxPortCntl <= 8'h00;
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SCTxPortWEn <= 1'b0;
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fifoReadEn <= 1'b0;
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SCTxPortReq <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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sendPacketRdy <= next_sendPacketRdy;
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sendPacketRdy <= next_sendPacketRdy;
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fifoReadEn <= next_fifoReadEn;
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SCTxPortReq <= next_SCTxPortReq;
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SCTxPortWEn <= next_SCTxPortWEn;
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SCTxPortData <= next_SCTxPortData;
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SCTxPortData <= next_SCTxPortData;
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SCTxPortCntl <= next_SCTxPortCntl;
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SCTxPortCntl <= next_SCTxPortCntl;
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SCTxPortWEn <= next_SCTxPortWEn;
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fifoReadEn <= next_fifoReadEn;
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SCTxPortReq <= next_SCTxPortReq;
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end
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end
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end
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end
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endmodule
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endmodule
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