| Line 59... |
Line 59... |
input RxOverflow;
|
input RxOverflow;
|
input [7:0]RxStatus;
|
input [7:0]RxStatus;
|
input RxTimeOut;
|
input RxTimeOut;
|
input SCGlobalEn;
|
input SCGlobalEn;
|
input sendPacketRdy;
|
input sendPacketRdy;
|
input [3:0]USBEndPControlReg;
|
input [4:0]USBEndPControlReg;
|
input [6:0]USBTgtAddress;
|
input [6:0]USBTgtAddress;
|
output clrEPRdy;
|
output clrEPRdy;
|
output endPMuxErrorsWEn;
|
output endPMuxErrorsWEn;
|
output [10:0]frameNum;
|
output [10:0]frameNum;
|
output getPacketREn;
|
output getPacketREn;
|
| Line 98... |
Line 98... |
reg sendPacketWEn, next_sendPacketWEn;
|
reg sendPacketWEn, next_sendPacketWEn;
|
reg SOFRxed, next_SOFRxed;
|
reg SOFRxed, next_SOFRxed;
|
reg stallSent, next_stallSent;
|
reg stallSent, next_stallSent;
|
reg transDone, next_transDone;
|
reg transDone, next_transDone;
|
reg [3:0]USBEndP, next_USBEndP;
|
reg [3:0]USBEndP, next_USBEndP;
|
wire [3:0]USBEndPControlReg;
|
wire [4:0]USBEndPControlReg;
|
reg [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
|
reg [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
|
reg [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
|
reg [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
|
wire [6:0]USBTgtAddress;
|
wire [6:0]USBTgtAddress;
|
|
|
// diagram signals declarations
|
// diagram signals declarations
|
| Line 123... |
Line 123... |
`define GET_TOKEN_CHK_SOF 5'b00110
|
`define GET_TOKEN_CHK_SOF 5'b00110
|
`define PID_ERROR 5'b00111
|
`define PID_ERROR 5'b00111
|
`define CHK_RDY 5'b01000
|
`define CHK_RDY 5'b01000
|
`define IN_NAK_STALL 5'b01001
|
`define IN_NAK_STALL 5'b01001
|
`define IN_CHK_RDY 5'b01010
|
`define IN_CHK_RDY 5'b01010
|
`define IN_DATA 5'b01011
|
`define SETUP_OUT_CHK 5'b01011
|
`define IN_GET_RESP 5'b01100
|
`define SETUP_OUT_SEND 5'b01100
|
`define SETUP_OUT_CHK 5'b01101
|
`define SETUP_OUT_GET_PKT 5'b01101
|
`define SETUP_OUT_SEND 5'b01110
|
`define START_S1 5'b01110
|
`define SETUP_OUT_GET_PKT 5'b01111
|
`define GET_TOKEN_DELAY 5'b01111
|
`define START_S1 5'b10000
|
`define GET_TOKEN_CHK_ADDR 5'b10000
|
`define GET_TOKEN_DELAY 5'b10001
|
`define IN_RESP_GET_RESP 5'b10001
|
`define GET_TOKEN_CHK_ADDR 5'b10010
|
`define IN_RESP_DATA 5'b10010
|
|
`define IN_RESP_CHK_ISO 5'b10011
|
|
|
reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
|
reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
|
|
|
|
|
// Machine: slvCntrl
|
// Machine: slvCntrl
|
| Line 195... |
Line 196... |
begin
|
begin
|
NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
|
NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
|
next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
|
next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
|
next_getPacketREn <= 1'b1;
|
next_getPacketREn <= 1'b1;
|
end
|
end
|
else if (PIDByte[3:0] == `IN)
|
else if ((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
|
begin
|
begin
|
NextState_slvCntrl <= `IN_CHK_RDY;
|
NextState_slvCntrl <= `IN_CHK_RDY;
|
next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
|
next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
|
end
|
end
|
|
else if (((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
|
|
begin
|
|
NextState_slvCntrl <= `IN_RESP_DATA;
|
|
next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
|
|
next_sendPacketWEn <= 1'b1;
|
|
next_sendPacketPID <= `DATA0;
|
|
end
|
|
else if ((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1))
|
|
begin
|
|
NextState_slvCntrl <= `IN_RESP_DATA;
|
|
next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
|
|
next_sendPacketWEn <= 1'b1;
|
|
next_sendPacketPID <= `DATA1;
|
|
end
|
|
else if (PIDByte[3:0] == `IN)
|
|
begin
|
|
NextState_slvCntrl <= `CHK_RDY;
|
|
next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
|
|
end
|
else
|
else
|
begin
|
begin
|
NextState_slvCntrl <= `PID_ERROR;
|
NextState_slvCntrl <= `PID_ERROR;
|
end
|
end
|
end
|
end
|
| Line 264... |
Line 284... |
end
|
end
|
end
|
end
|
`SETUP_OUT_GET_PKT:
|
`SETUP_OUT_GET_PKT:
|
begin
|
begin
|
next_getPacketREn <= 1'b0;
|
next_getPacketREn <= 1'b0;
|
if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
|
if ((getPacketRdy == 1'b1) && (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
|
|
begin
|
|
NextState_slvCntrl <= `CHK_RDY;
|
|
end
|
|
else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
|
bitStuffError == 1'b0 &&
|
bitStuffError == 1'b0 &&
|
RxOverflow == 1'b0 &&
|
RxOverflow == 1'b0 &&
|
RxTimeOut == 1'b0))
|
RxTimeOut == 1'b0))
|
begin
|
begin
|
NextState_slvCntrl <= `SETUP_OUT_CHK;
|
NextState_slvCntrl <= `SETUP_OUT_CHK;
|
| Line 302... |
Line 326... |
next_sendPacketPID <= `STALL;
|
next_sendPacketPID <= `STALL;
|
next_stallSent <= 1'b1;
|
next_stallSent <= 1'b1;
|
end
|
end
|
else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
|
else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
|
begin
|
begin
|
NextState_slvCntrl <= `IN_DATA;
|
NextState_slvCntrl <= `IN_RESP_DATA;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `DATA0;
|
next_sendPacketPID <= `DATA0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState_slvCntrl <= `IN_DATA;
|
NextState_slvCntrl <= `IN_RESP_DATA;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketWEn <= 1'b1;
|
next_sendPacketPID <= `DATA1;
|
next_sendPacketPID <= `DATA1;
|
end
|
end
|
end
|
end
|
`IN_DATA:
|
`IN_RESP_GET_RESP:
|
|
begin
|
|
next_getPacketREn <= 1'b0;
|
|
if (getPacketRdy == 1'b1)
|
|
begin
|
|
NextState_slvCntrl <= `CHK_RDY;
|
|
end
|
|
end
|
|
`IN_RESP_DATA:
|
begin
|
begin
|
next_sendPacketWEn <= 1'b0;
|
next_sendPacketWEn <= 1'b0;
|
if (sendPacketRdy == 1'b1)
|
if (sendPacketRdy == 1'b1)
|
begin
|
begin
|
NextState_slvCntrl <= `IN_GET_RESP;
|
NextState_slvCntrl <= `IN_RESP_CHK_ISO;
|
next_getPacketREn <= 1'b1;
|
|
end
|
end
|
end
|
end
|
`IN_GET_RESP:
|
`IN_RESP_CHK_ISO:
|
begin
|
begin
|
next_getPacketREn <= 1'b0;
|
if (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
|
if (getPacketRdy == 1'b1)
|
|
begin
|
begin
|
NextState_slvCntrl <= `CHK_RDY;
|
NextState_slvCntrl <= `CHK_RDY;
|
end
|
end
|
|
else
|
|
begin
|
|
NextState_slvCntrl <= `IN_RESP_GET_RESP;
|
|
next_getPacketREn <= 1'b1;
|
|
end
|
end
|
end
|
`START_S1:
|
`START_S1:
|
begin
|
begin
|
NextState_slvCntrl <= `WAIT_RX1;
|
NextState_slvCntrl <= `WAIT_RX1;
|
end
|
end
|
