| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
|
|
module usbHostSlave(
|
module usbHostSlave(
|
clk,
|
clk_i,
|
rst,
|
rst_i,
|
address_i,
|
address_i,
|
data_i,
|
data_i,
|
data_o,
|
data_o,
|
writeEn,
|
we_i,
|
strobe_i,
|
strobe_i,
|
ack_o,
|
ack_o,
|
|
usbClk,
|
hostSOFSentIntOut,
|
hostSOFSentIntOut,
|
hostConnEventIntOut,
|
hostConnEventIntOut,
|
hostResumeIntOut,
|
hostResumeIntOut,
|
hostTransDoneIntOut,
|
hostTransDoneIntOut,
|
slaveNAKSentIntOut,
|
slaveNAKSentIntOut,
|
| Line 77... |
Line 78... |
parameter EP2_FIFO_DEPTH = 64;
|
parameter EP2_FIFO_DEPTH = 64;
|
parameter EP2_FIFO_ADDR_WIDTH = 6;
|
parameter EP2_FIFO_ADDR_WIDTH = 6;
|
parameter EP3_FIFO_DEPTH = 64;
|
parameter EP3_FIFO_DEPTH = 64;
|
parameter EP3_FIFO_ADDR_WIDTH = 6;
|
parameter EP3_FIFO_ADDR_WIDTH = 6;
|
|
|
input clk;
|
input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz
|
input rst;
|
input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
|
input [7:0] address_i;
|
input [7:0] address_i; //Wishbone bus address in
|
input [7:0] data_i;
|
input [7:0] data_i; //Wishbone bus data in
|
output [7:0] data_o;
|
output [7:0] data_o; //Wishbone bus data out
|
input writeEn;
|
input we_i; //Wishbone bus write enable in
|
input strobe_i;
|
input strobe_i; //Wishbone bus strobe in
|
output ack_o;
|
output ack_o; //Wishbone bus acknowledge out
|
|
input usbClk; //usb clock. 48Mhz +/-0.25%
|
output hostSOFSentIntOut;
|
output hostSOFSentIntOut;
|
output hostConnEventIntOut;
|
output hostConnEventIntOut;
|
output hostResumeIntOut;
|
output hostResumeIntOut;
|
output hostTransDoneIntOut;
|
output hostTransDoneIntOut;
|
output slaveSOFRxedIntOut;
|
output slaveSOFRxedIntOut;
|
| Line 101... |
Line 103... |
output USBWireDataOutTick;
|
output USBWireDataOutTick;
|
output USBWireDataInTick;
|
output USBWireDataInTick;
|
output USBWireCtrlOut;
|
output USBWireCtrlOut;
|
output USBFullSpeed;
|
output USBFullSpeed;
|
|
|
wire clk;
|
wire clk_i;
|
wire rst;
|
wire rst_i;
|
wire [7:0] address_i;
|
wire [7:0] address_i;
|
wire [7:0] data_i;
|
wire [7:0] data_i;
|
wire [7:0] data_o;
|
wire [7:0] data_o;
|
wire writeEn;
|
wire we_i;
|
wire strobe_i;
|
wire strobe_i;
|
wire ack_o;
|
wire ack_o;
|
|
wire usbClk;
|
wire hostSOFSentIntOut;
|
wire hostSOFSentIntOut;
|
wire hostConnEventIntOut;
|
wire hostConnEventIntOut;
|
wire hostResumeIntOut;
|
wire hostResumeIntOut;
|
wire hostTransDoneIntOut;
|
wire hostTransDoneIntOut;
|
wire slaveSOFRxedIntOut;
|
wire slaveSOFRxedIntOut;
|
| Line 201... |
Line 204... |
wire slaveEP3RxFifoSel;
|
wire slaveEP3RxFifoSel;
|
wire slaveEP0TxFifoSel;
|
wire slaveEP0TxFifoSel;
|
wire slaveEP1TxFifoSel;
|
wire slaveEP1TxFifoSel;
|
wire slaveEP2TxFifoSel;
|
wire slaveEP2TxFifoSel;
|
wire slaveEP3TxFifoSel;
|
wire slaveEP3TxFifoSel;
|
|
wire rstSyncToBusClk;
|
|
wire rstSyncToUsbClk;
|
|
|
assign USBFullSpeed = fullSpeedBitRateToSIE;
|
assign USBFullSpeed = fullSpeedBitRateToSIE;
|
|
|
usbHostControl u_usbHostControl(
|
usbHostControl u_usbHostControl(
|
.clk(clk),
|
.busClk(clk_i),
|
.rst(rst),
|
.rstSyncToBusClk(rstSyncToBusClk),
|
|
.usbClk(usbClk),
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.TxFifoRE(hostTxFifoRE),
|
.TxFifoRE(hostTxFifoRE),
|
.TxFifoData(hostTxFifoData),
|
.TxFifoData(hostTxFifoData),
|
.TxFifoEmpty(hostTxFifoEmpty),
|
.TxFifoEmpty(hostTxFifoEmpty),
|
.RxFifoWE(hostRxFifoWE),
|
.RxFifoWE(hostRxFifoWE),
|
.RxFifoData(hostRxFifoData),
|
.RxFifoData(hostRxFifoData),
|
| Line 228... |
Line 235... |
.connectStateIn(connectState),
|
.connectStateIn(connectState),
|
.resumeDetectedIn(resumeDetected),
|
.resumeDetectedIn(resumeDetected),
|
.busAddress(address_i[3:0]),
|
.busAddress(address_i[3:0]),
|
.busDataIn(data_i),
|
.busDataIn(data_i),
|
.busDataOut(dataFromHostControl),
|
.busDataOut(dataFromHostControl),
|
.busWriteEn(writeEn),
|
.busWriteEn(we_i),
|
.busStrobe_i(strobe_i),
|
.busStrobe_i(strobe_i),
|
.SOFSentIntOut(hostSOFSentIntOut),
|
.SOFSentIntOut(hostSOFSentIntOut),
|
.connEventIntOut(hostConnEventIntOut),
|
.connEventIntOut(hostConnEventIntOut),
|
.resumeIntOut(hostResumeIntOut),
|
.resumeIntOut(hostResumeIntOut),
|
.transDoneIntOut(hostTransDoneIntOut),
|
.transDoneIntOut(hostTransDoneIntOut),
|
.hostControlSelect(hostControlSel) );
|
.hostControlSelect(hostControlSel) );
|
|
|
|
|
usbSlaveControl u_usbSlaveControl(
|
usbSlaveControl u_usbSlaveControl(
|
.clk(clk),
|
.busClk(clk_i),
|
.rst(rst),
|
.rstSyncToBusClk(rstSyncToBusClk),
|
|
.usbClk(usbClk),
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.RxByteStatus(RxCtrlOut),
|
.RxByteStatus(RxCtrlOut),
|
.RxData(RxDataFromSIE),
|
.RxData(RxDataFromSIE),
|
.RxDataValid(RxDataOutWEn),
|
.RxDataValid(RxDataOutWEn),
|
.SIERxTimeOut(noActivityTimeOut),
|
.SIERxTimeOut(noActivityTimeOut),
|
.RxFifoData(slaveRxFifoData),
|
.RxFifoData(slaveRxFifoData),
|
| Line 256... |
Line 265... |
.connectStateIn(connectState),
|
.connectStateIn(connectState),
|
.resumeDetectedIn(resumeDetected),
|
.resumeDetectedIn(resumeDetected),
|
.busAddress(address_i[4:0]),
|
.busAddress(address_i[4:0]),
|
.busDataIn(data_i),
|
.busDataIn(data_i),
|
.busDataOut(dataFromSlaveControl),
|
.busDataOut(dataFromSlaveControl),
|
.busWriteEn(writeEn),
|
.busWriteEn(we_i),
|
.busStrobe_i(strobe_i),
|
.busStrobe_i(strobe_i),
|
.SOFRxedIntOut(slaveSOFRxedIntOut),
|
.SOFRxedIntOut(slaveSOFRxedIntOut),
|
.resetEventIntOut(slaveResetEventIntOut),
|
.resetEventIntOut(slaveResetEventIntOut),
|
.resumeIntOut(slaveResumeIntOut),
|
.resumeIntOut(slaveResumeIntOut),
|
.transDoneIntOut(slaveTransDoneIntOut),
|
.transDoneIntOut(slaveTransDoneIntOut),
|
| Line 290... |
Line 299... |
|
|
wishBoneBI u_wishBoneBI (
|
wishBoneBI u_wishBoneBI (
|
.address(address_i),
|
.address(address_i),
|
.dataIn(data_i),
|
.dataIn(data_i),
|
.dataOut(data_o),
|
.dataOut(data_o),
|
.writeEn(writeEn),
|
.writeEn(we_i),
|
.strobe_i(strobe_i),
|
.strobe_i(strobe_i),
|
.ack_o(ack_o),
|
.ack_o(ack_o),
|
.clk(clk),
|
.clk(clk_i),
|
.rst(rst),
|
.rst(rstSyncToBusClk),
|
.hostControlSel(hostControlSel),
|
.hostControlSel(hostControlSel),
|
.hostRxFifoSel(hostRxFifoSel),
|
.hostRxFifoSel(hostRxFifoSel),
|
.hostTxFifoSel(hostTxFifoSel),
|
.hostTxFifoSel(hostTxFifoSel),
|
.slaveControlSel(slaveControlSel),
|
.slaveControlSel(slaveControlSel),
|
.slaveEP0RxFifoSel(slaveEP0RxFifoSel),
|
.slaveEP0RxFifoSel(slaveEP0RxFifoSel),
|
| Line 342... |
Line 351... |
.fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
|
.fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
|
.fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
|
.fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
|
.dataIn(data_i),
|
.dataIn(data_i),
|
.dataOut(dataFromHostSlaveMux),
|
.dataOut(dataFromHostSlaveMux),
|
.address(address_i[0]),
|
.address(address_i[0]),
|
.writeEn(writeEn),
|
.writeEn(we_i),
|
.strobe_i(strobe_i),
|
.strobe_i(strobe_i),
|
.clk(clk),
|
.usbClk(usbClk),
|
.rst(rst),
|
.busClk(clk_i),
|
.hostSlaveMuxSel(hostSlaveMuxSel) );
|
.hostSlaveMuxSel(hostSlaveMuxSel),
|
|
.rstFromWire(rst_i),
|
|
.rstSyncToBusClkOut(rstSyncToBusClk),
|
|
.rstSyncToUsbClkOut(rstSyncToUsbClk)
|
|
);
|
|
|
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
|
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
|
.clk(clk),
|
.clk(usbClk),
|
.rst(rst),
|
.rst(rstSyncToUsbClk),
|
.USBWireDataIn(USBWireDataIn),
|
.USBWireDataIn(USBWireDataIn),
|
.USBWireDataOut(USBWireDataOut),
|
.USBWireDataOut(USBWireDataOut),
|
.USBWireDataInTick(USBWireDataInTick),
|
.USBWireDataInTick(USBWireDataInTick),
|
.USBWireDataOutTick(USBWireDataOutTick),
|
.USBWireDataOutTick(USBWireDataOutTick),
|
.USBWireCtrlOut(USBWireCtrlOut),
|
.USBWireCtrlOut(USBWireCtrlOut),
|
| Line 372... |
Line 385... |
.noActivityTimeOut(noActivityTimeOut)
|
.noActivityTimeOut(noActivityTimeOut)
|
);
|
);
|
|
|
//---Host fifos
|
//---Host fifos
|
TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
|
TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
|
.clk(clk),
|
.usbClk(usbClk),
|
.rst(rst),
|
.busClk(clk_i),
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.fifoREn(hostTxFifoRE),
|
.fifoREn(hostTxFifoRE),
|
.fifoEmpty(hostTxFifoEmpty),
|
.fifoEmpty(hostTxFifoEmpty),
|
.busAddress(address_i[2:0]),
|
.busAddress(address_i[2:0]),
|
.busWriteEn(writeEn),
|
.busWriteEn(we_i),
|
.busStrobe_i(strobe_i),
|
.busStrobe_i(strobe_i),
|
.busFifoSelect(hostTxFifoSel),
|
.busFifoSelect(hostTxFifoSel),
|
.busDataIn(data_i),
|
.busDataIn(data_i),
|
.busDataOut(dataFromHostTxFifo),
|
.busDataOut(dataFromHostTxFifo),
|
.fifoDataOut(hostTxFifoData) );
|
.fifoDataOut(hostTxFifoData) );
|
|
|
|
|
RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
|
RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
|
.clk(clk),
|
.usbClk(usbClk),
|
.rst(rst),
|
.busClk(clk_i),
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.fifoWEn(hostRxFifoWE),
|
.fifoWEn(hostRxFifoWE),
|
.fifoFull(hostRxFifoFull),
|
.fifoFull(hostRxFifoFull),
|
.busAddress(address_i[2:0]),
|
.busAddress(address_i[2:0]),
|
.busWriteEn(writeEn),
|
.busWriteEn(we_i),
|
.busStrobe_i(strobe_i),
|
.busStrobe_i(strobe_i),
|
.busFifoSelect(hostRxFifoSel),
|
.busFifoSelect(hostRxFifoSel),
|
.busDataIn(data_i),
|
.busDataIn(data_i),
|
.busDataOut(dataFromHostRxFifo),
|
.busDataOut(dataFromHostRxFifo),
|
.fifoDataIn(hostRxFifoData) );
|
.fifoDataIn(hostRxFifoData) );
|
|
|
//---Slave fifos
|
//---Slave fifos
|
|
|
TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
|
TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
|
.clk(clk),
|
.usbClk(usbClk),
|
.rst(rst),
|
.busClk(clk_i),
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.fifoREn(TxFifoEP0REn),
|
.fifoREn(TxFifoEP0REn),
|
.fifoEmpty(TxFifoEP0Empty),
|
.fifoEmpty(TxFifoEP0Empty),
|
.busAddress(address_i[2:0]),
|
.busAddress(address_i[2:0]),
|
.busWriteEn(writeEn),
|
.busWriteEn(we_i),
|
.busStrobe_i(strobe_i),
|
.busStrobe_i(strobe_i),
|
.busFifoSelect(slaveEP0TxFifoSel),
|
.busFifoSelect(slaveEP0TxFifoSel),
|
.busDataIn(data_i),
|
.busDataIn(data_i),
|
.busDataOut(dataFromEP0TxFifo),
|
.busDataOut(dataFromEP0TxFifo),
|
.fifoDataOut(TxFifoEP0Data) );
|
.fifoDataOut(TxFifoEP0Data) );
|
|
|
TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
|
TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
|
.clk(clk),
|
.usbClk(usbClk),
|
.rst(rst),
|
.busClk(clk_i),
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.fifoREn(TxFifoEP1REn),
|
.fifoREn(TxFifoEP1REn),
|
.fifoEmpty(TxFifoEP1Empty),
|
.fifoEmpty(TxFifoEP1Empty),
|
.busAddress(address_i[2:0]),
|
.busAddress(address_i[2:0]),
|
.busWriteEn(writeEn),
|
.busWriteEn(we_i),
|
.busStrobe_i(strobe_i),
|
.busStrobe_i(strobe_i),
|
.busFifoSelect(slaveEP1TxFifoSel),
|
.busFifoSelect(slaveEP1TxFifoSel),
|
.busDataIn(data_i),
|
.busDataIn(data_i),
|
.busDataOut(dataFromEP1TxFifo),
|
.busDataOut(dataFromEP1TxFifo),
|
.fifoDataOut(TxFifoEP1Data) );
|
.fifoDataOut(TxFifoEP1Data) );
|
|
|
TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
|
TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
|
.clk(clk),
|
.usbClk(usbClk),
|
.rst(rst),
|
.busClk(clk_i),
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.fifoREn(TxFifoEP2REn),
|
.fifoREn(TxFifoEP2REn),
|
.fifoEmpty(TxFifoEP2Empty),
|
.fifoEmpty(TxFifoEP2Empty),
|
.busAddress(address_i[2:0]),
|
.busAddress(address_i[2:0]),
|
.busWriteEn(writeEn),
|
.busWriteEn(we_i),
|
.busStrobe_i(strobe_i),
|
.busStrobe_i(strobe_i),
|
.busFifoSelect(slaveEP2TxFifoSel),
|
.busFifoSelect(slaveEP2TxFifoSel),
|
.busDataIn(data_i),
|
.busDataIn(data_i),
|
.busDataOut(dataFromEP2TxFifo),
|
.busDataOut(dataFromEP2TxFifo),
|
.fifoDataOut(TxFifoEP2Data) );
|
.fifoDataOut(TxFifoEP2Data) );
|
|
|
TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
|
TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
|
.clk(clk),
|
.usbClk(usbClk),
|
.rst(rst),
|
.busClk(clk_i),
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.fifoREn(TxFifoEP3REn),
|
.fifoREn(TxFifoEP3REn),
|
.fifoEmpty(TxFifoEP3Empty),
|
.fifoEmpty(TxFifoEP3Empty),
|
.busAddress(address_i[2:0]),
|
.busAddress(address_i[2:0]),
|
.busWriteEn(writeEn),
|
.busWriteEn(we_i),
|
.busStrobe_i(strobe_i),
|
.busStrobe_i(strobe_i),
|
.busFifoSelect(slaveEP3TxFifoSel),
|
.busFifoSelect(slaveEP3TxFifoSel),
|
.busDataIn(data_i),
|
.busDataIn(data_i),
|
.busDataOut(dataFromEP3TxFifo),
|
.busDataOut(dataFromEP3TxFifo),
|
.fifoDataOut(TxFifoEP3Data) );
|
.fifoDataOut(TxFifoEP3Data) );
|
|
|
RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
|
RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
|
.clk(clk),
|
.usbClk(usbClk),
|
.rst(rst),
|
.busClk(clk_i),
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.fifoWEn(RxFifoEP0WEn),
|
.fifoWEn(RxFifoEP0WEn),
|
.fifoFull(RxFifoEP0Full),
|
.fifoFull(RxFifoEP0Full),
|
.busAddress(address_i[2:0]),
|
.busAddress(address_i[2:0]),
|
.busWriteEn(writeEn),
|
.busWriteEn(we_i),
|
.busStrobe_i(strobe_i),
|
.busStrobe_i(strobe_i),
|
.busFifoSelect(slaveEP0RxFifoSel),
|
.busFifoSelect(slaveEP0RxFifoSel),
|
.busDataIn(data_i),
|
.busDataIn(data_i),
|
.busDataOut(dataFromEP0RxFifo),
|
.busDataOut(dataFromEP0RxFifo),
|
.fifoDataIn(slaveRxFifoData) );
|
.fifoDataIn(slaveRxFifoData) );
|
|
|
RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
|
RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
|
.clk(clk),
|
.usbClk(usbClk),
|
.rst(rst),
|
.busClk(clk_i),
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.fifoWEn(RxFifoEP1WEn),
|
.fifoWEn(RxFifoEP1WEn),
|
.fifoFull(RxFifoEP1Full),
|
.fifoFull(RxFifoEP1Full),
|
.busAddress(address_i[2:0]),
|
.busAddress(address_i[2:0]),
|
.busWriteEn(writeEn),
|
.busWriteEn(we_i),
|
.busStrobe_i(strobe_i),
|
.busStrobe_i(strobe_i),
|
.busFifoSelect(slaveEP1RxFifoSel),
|
.busFifoSelect(slaveEP1RxFifoSel),
|
.busDataIn(data_i),
|
.busDataIn(data_i),
|
.busDataOut(dataFromEP1RxFifo),
|
.busDataOut(dataFromEP1RxFifo),
|
.fifoDataIn(slaveRxFifoData) );
|
.fifoDataIn(slaveRxFifoData) );
|
|
|
RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
|
RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
|
.clk(clk),
|
.usbClk(usbClk),
|
.rst(rst),
|
.busClk(clk_i),
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.fifoWEn(RxFifoEP2WEn),
|
.fifoWEn(RxFifoEP2WEn),
|
.fifoFull(RxFifoEP2Full),
|
.fifoFull(RxFifoEP2Full),
|
.busAddress(address_i[2:0]),
|
.busAddress(address_i[2:0]),
|
.busWriteEn(writeEn),
|
.busWriteEn(we_i),
|
.busStrobe_i(strobe_i),
|
.busStrobe_i(strobe_i),
|
.busFifoSelect(slaveEP2RxFifoSel),
|
.busFifoSelect(slaveEP2RxFifoSel),
|
.busDataIn(data_i),
|
.busDataIn(data_i),
|
.busDataOut(dataFromEP2RxFifo),
|
.busDataOut(dataFromEP2RxFifo),
|
.fifoDataIn(slaveRxFifoData) );
|
.fifoDataIn(slaveRxFifoData) );
|
|
|
RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
|
RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
|
.clk(clk),
|
.usbClk(usbClk),
|
.rst(rst),
|
.busClk(clk_i),
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
.fifoWEn(RxFifoEP3WEn),
|
.fifoWEn(RxFifoEP3WEn),
|
.fifoFull(RxFifoEP3Full),
|
.fifoFull(RxFifoEP3Full),
|
.busAddress(address_i[2:0]),
|
.busAddress(address_i[2:0]),
|
.busWriteEn(writeEn),
|
.busWriteEn(we_i),
|
.busStrobe_i(strobe_i),
|
.busStrobe_i(strobe_i),
|
.busFifoSelect(slaveEP3RxFifoSel),
|
.busFifoSelect(slaveEP3RxFifoSel),
|
.busDataIn(data_i),
|
.busDataIn(data_i),
|
.busDataOut(dataFromEP3RxFifo),
|
.busDataOut(dataFromEP3RxFifo),
|
.fifoDataIn(slaveRxFifoData) );
|
.fifoDataIn(slaveRxFifoData) );
|
