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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: usbHostSlave.v,v 1.2 2004-12-18 14:36:23 sfielding Exp $
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`timescale 1ns / 1ps
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2004/10/11 04:01:11 sfielding
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// Created
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//
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//
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module usbHostSlave(
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module usbHostSlave(
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clk,
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clk,
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rst,
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rst,
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address_i,
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address_i,
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Line 63... |
slaveTransDoneIntOut,
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slaveTransDoneIntOut,
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USBWireDataIn,
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USBWireDataIn,
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USBWireDataInTick,
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USBWireDataInTick,
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USBWireDataOut,
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USBWireDataOut,
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USBWireDataOutTick,
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USBWireDataOutTick,
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USBWireCtrlOut
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USBWireCtrlOut,
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USBFullSpeed
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);
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);
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parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
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parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
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parameter HOST_FIFO_ADDR_WIDTH = 6;
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parameter HOST_FIFO_ADDR_WIDTH = 6;
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parameter EP0_FIFO_DEPTH = 64;
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parameter EP0_FIFO_DEPTH = 64;
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parameter EP0_FIFO_ADDR_WIDTH = 6;
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parameter EP0_FIFO_ADDR_WIDTH = 6;
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Line 99... |
input [1:0] USBWireDataIn;
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input [1:0] USBWireDataIn;
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output [1:0] USBWireDataOut;
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output [1:0] USBWireDataOut;
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output USBWireDataOutTick;
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output USBWireDataOutTick;
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output USBWireDataInTick;
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output USBWireDataInTick;
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output USBWireCtrlOut;
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output USBWireCtrlOut;
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output USBFullSpeed;
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wire clk;
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wire clk;
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wire rst;
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wire rst;
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wire [7:0] address_i;
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wire [7:0] address_i;
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wire [7:0] data_i;
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wire [7:0] data_i;
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Line 123... |
wire [1:0] USBWireDataIn;
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wire [1:0] USBWireDataIn;
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wire [1:0] USBWireDataOut;
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wire [1:0] USBWireDataOut;
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wire USBWireDataOutTick;
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wire USBWireDataOutTick;
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wire USBWireDataInTick;
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wire USBWireDataInTick;
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wire USBWireCtrlOut;
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wire USBWireCtrlOut;
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wire USBFullSpeed;
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//internal wiring
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//internal wiring
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wire hostControlSel;
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wire hostControlSel;
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wire slaveControlSel;
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wire slaveControlSel;
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wire hostRxFifoSel;
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wire hostRxFifoSel;
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Line 202... |
wire slaveEP0TxFifoSel;
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wire slaveEP0TxFifoSel;
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wire slaveEP1TxFifoSel;
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wire slaveEP1TxFifoSel;
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wire slaveEP2TxFifoSel;
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wire slaveEP2TxFifoSel;
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wire slaveEP3TxFifoSel;
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wire slaveEP3TxFifoSel;
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assign USBFullSpeed = fullSpeedBitRateToSIE;
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usbHostControl u_usbHostControl(
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usbHostControl u_usbHostControl(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.TxFifoRE(hostTxFifoRE),
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.TxFifoRE(hostTxFifoRE),
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.TxFifoData(hostTxFifoData),
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.TxFifoData(hostTxFifoData),
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Line 341... |
.fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
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.fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
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.fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
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.fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
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.fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
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.fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
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.dataIn(data_i),
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.dataIn(data_i),
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.dataOut(dataFromHostSlaveMux),
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.dataOut(dataFromHostSlaveMux),
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.address(address_i[0]),
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.writeEn(writeEn),
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.writeEn(writeEn),
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.strobe_i(strobe_i),
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.strobe_i(strobe_i),
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.hostSlaveMuxSel(hostSlaveMuxSel) );
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.hostSlaveMuxSel(hostSlaveMuxSel) );
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