URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [wrapper/] [usbSlave.v] - Diff between revs 40 and 43

Rev 40	Rev 43
Line 192...	Line 192...
`wire rstSyncToUsbClk;`	`wire rstSyncToUsbClk;`
`wire noActivityTimeOutEnableToSIE;`	`wire noActivityTimeOutEnableToSIE;`
`wire noActivityTimeOutEnableFromHost;`	`wire noActivityTimeOutEnableFromHost;`
`wire noActivityTimeOutEnableFromSlave;`	`wire noActivityTimeOutEnableFromSlave;`

`assign USBFullSpeed = fullSpeedBitRateToSIE;`	`// This is not a bug.`
	`// USBFullSpeed controls the PHY edge speed.`
	`// The only time that the PHY needs to operate with low speed edge rate is`
	`// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity`
	`// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low`
	`// but according to spec edge speed must be full rate edge speed.`
	`assign USBFullSpeed = fullSpeedPolarityToSIE;`
	`//assign USBFullSpeed = fullSpeedBitRateToSIE;`
`assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);`	`assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);`
`assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);`	`assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);`

`usbSlaveControl u_usbSlaveControl(`	`usbSlaveControl u_usbSlaveControl(`
`.busClk(clk_i),`	`.busClk(clk_i),`