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// during migration to ActiveHDL 7.1. Released SystemC test bench.
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// during migration to ActiveHDL 7.1. Released SystemC test bench.
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// Re-generated .v files using ActiveHDL 7.1
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// Re-generated .v files using ActiveHDL 7.1
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// Replaced individual timescale directives with `include "timescale.v
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// Replaced individual timescale directives with `include "timescale.v
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// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to
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// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to
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// 'usbHostSlaveAvalonWrap'
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// 'usbHostSlaveAvalonWrap'
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// Version 1.3 - March 22nd 2008. Fixed bug in 'readUSBWireData'. Added
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// synchronizer to incoming USB wire data to avoid
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// metastability, and delay hazards. Not entirely sure, but it appears that
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// this bug caused more problems with some of the newer low power FPGAs
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// Maybe because they are more prone to problems with metastable
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// inputs that feed logic functions causing excessive high speed
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// toggle activity, and disrupting nearby cicuits.
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// Version 2.0 - June 16th 2008. Added two new top level modules which
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// allow the instantiation of only host (usbHost.v), or only device
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// features. Added double sync stages between usbClk, and busClk domains
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// to fix possible metastability issues. Also modified synchronization to
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// allow operation with busClk frequency less than usbClk frequency (down to
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// 24MHz). Integrated full support for USB PHY. Prior to this modification
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// the user would need to instantiate a GPIO module to control USB speed,
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// D+ and D- pull-up control, and VBUS detect. Fixed bug in bus interface wb_ack.
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// Modified cross-clock synchronisation of fifo resets
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// Added usbDevice, a standalone usb device implementation of usbhostslave
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// no additional hardware or software required
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