OpenCores
URL https://opencores.org/ocsvn/utosnet/utosnet/trunk

Subversion Repositories utosnet

[/] [utosnet/] [trunk/] [gateware/] [uTosNet_example/] [uTosNet_spi/] [uTosNet_spi.vhd] - Diff between revs 3 and 4

Show entire file | Details | Blame | View Log

Rev 3 Rev 4
Line 3... Line 3...
-- Engineer:            Simon Falsig
-- Engineer:            Simon Falsig
-- 
-- 
-- Create Date:         19/3/2010 
-- Create Date:         19/3/2010 
-- Design Name:         uTosNet
-- Design Name:         uTosNet
-- Module Name:         uTosNet_spi - Behavioral 
-- Module Name:         uTosNet_spi - Behavioral 
 
-- File Name:           utosnet_spi.vhd
-- Project Name:        uTosNet
-- Project Name:        uTosNet
-- Target Devices:      SDU XC3S50AN Board
-- Target Devices:      SDU XC3S50AN Board
-- Tool versions:       Xilinx ISE 11.4
-- Tool versions:       Xilinx ISE 11.4
-- Description:         PseudoTosNet is designed to provide an interface similar to 
-- Description:         PseudoTosNet is designed to provide an interface similar to 
--                                      the full-blown TosNet core, but usable on the SDU XC3S50AN 
--                                      the full-blown TosNet core, but usable on the SDU XC3S50AN 
Line 17... Line 18...
--                                      device.
--                                      device.
--
--
-- Revision: 
-- Revision: 
-- Revision 0.10 -      Initial release
-- Revision 0.10 -      Initial release
--
--
 
-- Copyright 2010
 
--
 
-- This module is free software: you can redistribute it and/or modify
 
-- it under the terms of the GNU Lesser General Public License as published by
 
-- the Free Software Foundation, either version 3 of the License, or
 
-- (at your option) any later version.
 
--
 
-- This module is distributed in the hope that it will be useful,
 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
-- GNU Lesser General Public License for more details.
 
--
 
-- You should have received a copy of the GNU Lesser General Public License
 
-- along with this module.  If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
 
 
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.