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-- Engineer: Simon Falsig
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-- Engineer: Simon Falsig
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--
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--
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-- Create Date: 19/03/2010
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-- Create Date: 19/03/2010
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-- Design Name: uTosNet_uart Example
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-- Design Name: uTosNet_uart Example
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-- Module Name: top - Behavioral
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-- Module Name: top - Behavioral
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-- File Name: top.vhd
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-- Project Name: uTosNet
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-- Project Name: uTosNet
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-- Target Devices: SDU XC3S50AN Board
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-- Target Devices: SDU XC3S50AN Board
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-- Tool versions: Xilinx ISE 11.4
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-- Tool versions: Xilinx ISE 11.4
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-- Description: This is a simple example showing the use of the uTosNet_uart
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-- Description: This is a simple example showing the use of the uTosNet_uart
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-- module.
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-- module.
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.10 - Initial release
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-- Revision 0.10 - Initial release
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--
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--
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-- Copyright 2010
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--
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-- This file is part of the uTosNet_spi Example
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--
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-- The uTosNet_uart Example is free software: you can redistribute it
|
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-- and/or modify it under the terms of the GNU Lesser General Public License as
|
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-- published by the Free Software Foundation, either version 3 of the License,
|
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-- or (at your option) any later version.
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--
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-- The uTosNet_uart Example is distributed in the hope that it will be
|
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-- useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
|
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
|
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-- along with the uTosNet_uart Example. If not, see
|
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-- <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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