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Line 34... |
end pr;
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end pr;
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architecture rtl of pr is
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architecture rtl of pr is
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constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PR no operation
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constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PR no operation
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constant PLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PR load
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constant PLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PR load
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constant FLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- NVZC load
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constant FLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- NZ load
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constant SEC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- 1 => C
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constant FLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- NZC load
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constant CLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- 0 => C
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constant FLV_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- NVZC load
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constant SEI_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- 1 => I
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constant SEC_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- 1 => C
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constant CLI_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- 0 => I
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constant CLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- 0 => C
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constant SED_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- 1 => D
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constant SEI_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- 1 => I
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constant CLD_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- 0 => D
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constant CLI_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- 0 => I
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constant CLV_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- 0 => V
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constant SED_P: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- 1 => D
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constant AUC_P: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- auc => ACR
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constant CLD_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- 0 => D
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constant HAC_P: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- hold ACR
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constant CLV_P: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- 0 => V
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constant SID_P: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- 1 => I/D
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constant AUC_P: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- auc => ACR
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constant LDZ_P: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- Z load
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constant HAC_P: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- hold ACR
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constant SID_P: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- 1 => I/D
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constant LDZ_P: STD_LOGIC_VECTOR(3 downto 0) := "1111"; -- Z load
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signal reg: STD_LOGIC_VECTOR(7 downto 0);
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signal reg: STD_LOGIC_VECTOR(7 downto 0);
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signal acr: STD_LOGIC; -- carry/borrow used for effectve address calculation
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signal acr: STD_LOGIC; -- carry/borrow used for effectve address calculation
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signal i_so: STD_LOGIC;
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signal i_so: STD_LOGIC;
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case fc is
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case fc is
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when PLD_P => reg(7 downto 6) <= din(7 downto 6); -- load NV1BDIZC
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when PLD_P => reg(7 downto 6) <= din(7 downto 6); -- load NV1BDIZC
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reg(5) <= '1';
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reg(5) <= '1';
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reg(4 downto 0) <= din(4 downto 0);
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reg(4 downto 0) <= din(4 downto 0);
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acr <= '0';
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acr <= '0';
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when FLD_P => reg <= n & v & '1' & reg(4 downto 2) & z & c; -- load NVZC
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when FLD_P => reg <= n & reg(6) & '1' & reg(4 downto 2) & z & reg(0); -- load NZ
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acr <= '0';
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when FLC_P => reg <= n & reg(6) & '1' & reg(4 downto 2) & z & c; -- load NZC
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acr <= '0';
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when FLV_P => reg <= n & v & '1' & reg(4 downto 2) & z & c; -- load NZCV
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acr <= '0';
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acr <= '0';
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when SEC_P => reg <= reg or "00000001"; -- 1 => C
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when SEC_P => reg <= reg or "00000001"; -- 1 => C
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acr <= acr;
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acr <= acr;
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when CLC_P => reg <= reg and "11111110"; -- 0 => C
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when CLC_P => reg <= reg and "11111110"; -- 0 => C
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acr <= acr;
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acr <= acr;
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