| Line 1... |
Line 1... |
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
-- 8 bit microprocessor (65C816) VHDL project --
|
-- 8/16 bit microprocessor (65C816) VHDL project --
|
-- Full RTL synchronous pipelined architecture --
|
-- Full RTL synchronous pipelined architecture --
|
-- Project by Valerio Venturi (Italy) --
|
-- Project by Valerio Venturi (Italy) --
|
-- Date: 5/04/2020 --
|
-- Start date: 5/04/2020 --
|
-- Last revision: 5/04/2020 --
|
-- Last revision: 5/04/2023 --
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
|
|
-- I don't makes any claims, promises or guarantees about the accuracy, completeness, or
|
|
-- adequacy of the contents of this website and expressly disclaims liability for errors and
|
|
-- omissions in the contents of this website. No warranty of any kind, implied, expressed or statutory,
|
|
-- including to fitness for a particular purpose and freedom from computer virus, is given with respect to
|
|
-- the contents of this website or its hyperlinks to other Internet resources.
|
|
-- Reference in this website to any specific commercial products, processes, or services, or
|
|
-- the use of any trade, firm or corporation name is for the information, and does
|
|
-- not constitute endorsement, recommendation, or favoring by me.
|
|
-- All the source code and tutorials are to be used on your own risk. All the ideas and views in this site are my own and
|
|
-- are not by any means related to my past or current employers.
|
|
|
|
You can use the codes given in this website for non-commercial purposes without my permission. But if you are using it for commercial purposes then contact me with the details of your project for my permission.
|
You can use the codes given in this website for non-commercial purposes without my permission. But if you are using it for commercial purposes then contact me with the details of your project for my permission.
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.std_logic_1164.all; -- defines std_logic types
|
use IEEE.std_logic_1164.all; -- defines std_logic types
|
