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-- 8 bit microprocessor (65C816) VHDL project --
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-- 8/16 bit microprocessor (65C816) VHDL project --
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-- Full RTL synchronous pipelined architecture --
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-- Full RTL synchronous pipelined architecture --
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-- Project by Valerio Venturi (Italy) --
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-- Project by Valerio Venturi (Italy) --
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-- Date: 5/04/2020 --
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-- Start date: 5/04/2020 --
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-- Last revision: 5/04/2020 --
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-- Last revision: 5/04/2023 --
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-- I don't makes any claims, promises or guarantees about the accuracy, completeness, or
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-- adequacy of the contents of this website and expressly disclaims liability for errors and
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-- omissions in the contents of this website. No warranty of any kind, implied, expressed or statutory,
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-- including to fitness for a particular purpose and freedom from computer virus, is given with respect to
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-- the contents of this website or its hyperlinks to other Internet resources.
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-- Reference in this website to any specific commercial products, processes, or services, or
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-- the use of any trade, firm or corporation name is for the information, and does
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-- not constitute endorsement, recommendation, or favoring by me.
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-- All the source code and tutorials are to be used on your own risk. All the ideas and views in this site are my own and
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-- are not by any means related to my past or current employers.
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You can use the codes given in this website for non-commercial purposes without my permission. But if you are using it for commercial purposes then contact me with the details of your project for my permission.
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You can use the codes given in this website for non-commercial purposes without my permission. But if you are using it for commercial purposes then contact me with the details of your project for my permission.
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all; -- defines std_logic types
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use IEEE.std_logic_1164.all; -- defines std_logic types
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