URL
https://opencores.org/ocsvn/verilog_fixed_point_math_library/verilog_fixed_point_math_library/trunk
Show entire file |
Details |
Blame |
View Log
Rev 8 |
Rev 9 |
Line 1... |
Line 1... |
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
//////////////////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////////////////
|
// Company:
|
// Company: Burke
|
// Engineer:
|
// Engineer: Tom Burke
|
//
|
//
|
// Create Date: 19:39:14 08/24/2011
|
// Create Date: 19:39:14 08/24/2011
|
// Design Name:
|
// Design Name:
|
// Module Name: divider
|
// Module Name: qdiv.v
|
// Project Name:
|
// Project Name: Fixed-point Math Library (Verilog)
|
// Target Devices:
|
// Target Devices:
|
// Tool versions:
|
// Tool versions: Xilinx ISE WebPack v14.7
|
// Description:
|
// Description: Fixed-point division in (Q,N) format
|
//
|
//
|
// Dependencies:
|
// Dependencies:
|
//
|
//
|
// Revision:
|
// Revision:
|
// Revision 0.01 - File Created
|
// Revision 0.01 - File Created
|
|
// Revision 0.02 - 25 May 2014
|
|
// Updated to fix an error
|
|
//
|
// Additional Comments: Based on my description on youtube:
|
// Additional Comments: Based on my description on youtube:
|
// http://youtu.be/TEnaPMYiuR8
|
// http://youtu.be/TEnaPMYiuR8
|
//
|
//
|
//////////////////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////////////////
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.