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/***********************************************************************
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*
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* This file is a part of the Rachael SPARC project accessible at
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* https://www.rachaelsparc.org. Unless otherwise noted code is released
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* under the Lesser GPL (LGPL) available at http://www.gnu.org.
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*
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* Copyright (c) 2005:
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* Michael Cowell
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*
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* Rachael SPARC is based heavily upon the LEON SPARC microprocessor
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* released by Gaisler Research, at http://www.gaisler.com, under the
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* LGPL. Much of the architectural work on Rachael was done by g2
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* Microsystems. Contact michael.cowell@g2microsystems.com for more
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* information.
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*
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***********************************************************************
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* $Id: test.vs,v 1.1 2008-10-10 21:03:35 julius Exp $
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* $URL: $
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* $Rev: $
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* $Author: julius $
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**********************************************************************
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*
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* Test Verilog file
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*
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**********************************************************************/
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`sinclude "test.struct"
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module test (
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// Inputs
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clk, reset, pie, pie2
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);
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input clk;
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input reset;
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input memory_bus pie2;
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input dual_bus pie;
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wire dual_bus db1;
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reg complex a;
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reg memory_bus mb1;
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wire dual_bus db2 = db1;
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reg [4:1] memory_bus mb2;
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reg [4:1] memory_bus mb5;
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reg [4:1] memory_bus mb6;
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wire memory_bus mb3 = mb2[1];
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assign db2.primary.req = 1'b1, db2.primary.address[31:28] = 4'h4;
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assign db2.primary.address[31:28] = 4'h4;
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always @(posedge clk or posedge db2.primary.req
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or db2.secondary.address or mb2[1]) begin
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mb1.address <= 32'h12348765;
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begin assign mb2[1].req = 1'b1;
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force mb2[2].req = 1'b1;
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assign thing = mb6[2].address[16:0];
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release mb2[2].req;
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end
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end
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wire [3:0] memory_bus mb2;
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fake_module fake_inst2 (mb2[1], db1, db1.primary.req,
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db1.primary.address[1], mb2[1].req);
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fake_module fake_inst ( . port1 ( mb2[1] ) ,
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.port2 (db1),
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.port3 (mb2[2]),
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.port4 (db1.primary.req),
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.port5 (db1.primary.address[1]),
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.port6 (mb2[1].req));
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assign mb2[3].req = 1'b1;
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wire [15:0] temp;
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wire [1:0] dual_bus db3;
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assign temp = mb2[2].address[15:0], temp = db2[2].primary.data[4:3];
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assign p=q, db3[2] =db2 , q=p;
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//assign mb2[2].address[15:0] = 16'h00;
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always @(posedge clk) begin
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if (mb2[3].primary == 1'b1)
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temp = mb5[3].address[15:0];
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while (mb2[1].address[1] == 1'b1)
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#1;
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case (mb2[1].req)
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1'b1: temp <= 4'h1;
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1'b0: begin
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temp <= 4'h1;
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case (mb2[2].req)
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1'b1: temp <= 4'h2;
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endcase // case(mb2[2].req)
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end
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mb2[3].req, mb2[4].req: temp <= 4'hx;
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endcase // case(mb2[1].req)
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for (mb1.req = 1'b1; mb1.req < db1[1].primary.address[15]; mb2[1].req++)
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temp <= 1'b1;
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sometask(mb1.req);
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end
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endmodule
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/* */
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