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https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [async_fifo_dw_simplex_actel.v] - Diff between revs 30 and 31
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Rev 30 |
Rev 31 |
Line 356... |
Line 356... |
# ( .length(addr_width))
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# ( .length(addr_width))
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fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
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fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
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adr_gen
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adr_gen
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# (.length(addr_width))
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# (.length(addr_width))
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fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clkt));
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fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
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// mux read or write adr to DPRAM
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// mux read or write adr to DPRAM
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assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
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assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
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assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
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assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
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