| Line 34... |
Line 34... |
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// adr_gen
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// adr_gen
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wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
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wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
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wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
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wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
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// dpram
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// dpram
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wire [addr_width:1] a_dpram_adr, b_dpram_adr;
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wire [addr_width:0] a_dpram_adr, b_dpram_adr;
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adr_gen
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adr_gen
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# ( .length(addr_width))
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# ( .length(addr_width))
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fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
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fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
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| Line 53... |
Line 53... |
adr_gen
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adr_gen
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# (.length(addr_width))
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# (.length(addr_width))
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fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_rst));
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fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_rst));
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// mux read or write adr to DPRAM
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// mux read or write adr to DPRAM
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assign a_dpram_adr = (a_wr) ? a_wadr_bin : a_radr_bin;
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assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
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assign b_dpram_adr = (b_wr) ? b_wadr_bin : b_radr_bin;
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assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
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vfifo_dual_port_ram_dc_dw
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vfifo_dual_port_ram_dc_dw
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# (.DATA_WIDTH(data_width), .ADDR_WIDTH(addr_width))
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# (.DATA_WIDTH(data_width), .ADDR_WIDTH(addr_width+1))
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dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
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dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
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.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
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.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
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versatile_fifo_async_cmp
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versatile_fifo_async_cmp
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# (.ADDR_WIDTH(addr_width))
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# (.ADDR_WIDTH(addr_width))
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