URL
https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 22 |
Rev 23 |
| Line 8... |
Line 8... |
parameter a_hi_size = 4;
|
parameter a_hi_size = 4;
|
parameter a_lo_size = 4;
|
parameter a_lo_size = 4;
|
parameter nr_of_queues = 16;
|
parameter nr_of_queues = 16;
|
parameter data_width = 36;
|
parameter data_width = 36;
|
|
|
input [data_width*nr_of_queues-1:0] d;
|
input [data_width-1:0] d;
|
output [0:nr_of_queues-1] fifo_full;
|
output [0:nr_of_queues-1] fifo_full;
|
input [0:nr_of_queues-1] write;
|
input [0:nr_of_queues-1] write;
|
input clk1;
|
input clk1;
|
input rst1;
|
input rst1;
|
|
|
| Line 93... |
Line 93... |
for (k=0;k<nr_of_queues;k=k+1) begin
|
for (k=0;k<nr_of_queues;k=k+1) begin
|
radr = (fifo_radr_bin[k] & {a_lo_size{read[k]}}) | radr;
|
radr = (fifo_radr_bin[k] & {a_lo_size{read[k]}}) | radr;
|
end
|
end
|
end
|
end
|
|
|
// and-or mux write data
|
|
generate
|
|
for (i=0;i<nr_of_queues;i=i+1) begin : vector2array
|
|
assign wdataa[i] = d[(nr_of_queues-i)*data_width-1:(nr_of_queues-1-i)*data_width];
|
|
end
|
|
endgenerate
|
|
|
|
always @*
|
|
begin
|
|
wdata = {data_width{1'b0}};
|
|
for (l=0;l<nr_of_queues;l=l+1) begin
|
|
wdata = (wdataa[l] & {data_width{write[l]}}) | wdata;
|
|
end
|
|
end
|
|
|
|
vfifo_dual_port_ram_dc_sw # ( .DATA_WIDTH(data_width), .ADDR_WIDTH(a_hi_size+a_lo_size))
|
vfifo_dual_port_ram_dc_sw # ( .DATA_WIDTH(data_width), .ADDR_WIDTH(a_hi_size+a_lo_size))
|
dpram (
|
dpram (
|
.d_a(wdata),
|
.d_a(d),
|
.adr_a({onehot2bin(write),wadr}),
|
.adr_a({onehot2bin(write),wadr}),
|
.we_a(|(write)),
|
.we_a(|(write)),
|
.clk_a(clk1),
|
.clk_a(clk1),
|
.q_b(q),
|
.q_b(q),
|
.adr_b({onehot2bin(read),radr}),
|
.adr_b({onehot2bin(read),radr}),
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.