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// async FIFO with multiple queues, multiple data
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// async FIFO with multiple queues, multiple data
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module async_fifo_mq_md (
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module async_fifo_mq_md (
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d, fifo_full, write, clk1, rst1,
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d, fifo_full, write, write_enable, clk1, rst1,
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q, fifo_empty, read, clk2, rst2
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q, fifo_empty, read, read_enable, clk2, rst2
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);
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);
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parameter a_hi_size = 4;
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parameter a_hi_size = 4;
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parameter a_lo_size = 4;
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parameter a_lo_size = 4;
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parameter nr_of_queues = 16;
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parameter nr_of_queues = 16;
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parameter data_width = 36;
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parameter data_width = 36;
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input [data_width*nr_of_queues-1:0] d;
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input [data_width*nr_of_queues-1:0] d;
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output [0:nr_of_queues-1] fifo_full;
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output [0:nr_of_queues-1] fifo_full;
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input [0:nr_of_queues-1] write;
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input write;
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input [0:nr_of_queues-1] write_enable;
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input clk1;
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input clk1;
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input rst1;
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input rst1;
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output [data_width-1:0] q;
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output [data_width-1:0] q;
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output [0:nr_of_queues-1] fifo_empty;
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output [0:nr_of_queues-1] fifo_empty;
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inout [0:nr_of_queues-1] read;
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input read;
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input [0:nr_of_queues-1] read_enable;
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input clk2;
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input clk2;
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input rst2;
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input rst2;
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wire [a_lo_size-1:0] fifo_wadr_bin[0:nr_of_queues-1];
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wire [a_lo_size-1:0] fifo_wadr_bin[0:nr_of_queues-1];
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wire [a_lo_size-1:0] fifo_wadr_gray[0:nr_of_queues-1];
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wire [a_lo_size-1:0] fifo_wadr_gray[0:nr_of_queues-1];
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generate
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generate
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for (i=0;i<nr_of_queues;i=i+1) begin : fifo_adr
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for (i=0;i<nr_of_queues;i=i+1) begin : fifo_adr
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gray_counter wadrcnt (
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gray_counter wadrcnt (
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.cke(write[i]),
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.cke(write & write_enable[i]),
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.q(fifo_wadr_gray[i]),
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.q(fifo_wadr_gray[i]),
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.q_bin(fifo_wadr_bin[i]),
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.q_bin(fifo_wadr_bin[i]),
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.rst(rst1),
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.rst(rst1),
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.clk(clk1));
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.clk(clk1));
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gray_counter radrcnt (
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gray_counter radrcnt (
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.cke(read[i]),
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.cke(read & read_enable[i]),
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.q(fifo_radr_gray[i]),
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.q(fifo_radr_gray[i]),
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.q_bin(fifo_radr_bin[i]),
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.q_bin(fifo_radr_bin[i]),
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.rst(rst2),
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.rst(rst2),
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.clk(clk2));
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.clk(clk2));
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// and-or mux write address
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// and-or mux write address
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always @*
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always @*
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begin
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begin
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wadr = {a_lo_size{1'b0}};
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wadr = {a_lo_size{1'b0}};
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for (j=0;j<nr_of_queues;j=j+1) begin
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for (j=0;j<nr_of_queues;j=j+1) begin
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wadr = (fifo_wadr_bin[j] & {a_lo_size{write[j]}}) | wadr;
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wadr = (fifo_wadr_bin[j] & {a_lo_size{write_enable[j]}}) | wadr;
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end
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end
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end
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end
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// and-or mux read address
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// and-or mux read address
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always @*
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always @*
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begin
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begin
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radr = {a_lo_size{1'b0}};
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radr = {a_lo_size{1'b0}};
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for (k=0;k<nr_of_queues;k=k+1) begin
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for (k=0;k<nr_of_queues;k=k+1) begin
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radr = (fifo_radr_bin[k] & {a_lo_size{read[k]}}) | radr;
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radr = (fifo_radr_bin[k] & {a_lo_size{read_enable[k]}}) | radr;
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end
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end
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end
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end
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// and-or mux write data
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// and-or mux write data
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generate
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generate
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always @*
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always @*
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begin
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begin
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wdata = {data_width{1'b0}};
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wdata = {data_width{1'b0}};
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for (l=0;l<nr_of_queues;l=l+1) begin
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for (l=0;l<nr_of_queues;l=l+1) begin
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wdata = (wdataa[l] & {data_width{write[l]}}) | wdata;
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wdata = (wdataa[l] & {data_width{write_enable[l]}}) | wdata;
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end
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end
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end
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end
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vfifo_dual_port_ram_dc_sw # ( .DATA_WIDTH(data_width), .ADDR_WIDTH(a_hi_size+a_lo_size))
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vfifo_dual_port_ram_dc_sw # ( .DATA_WIDTH(data_width), .ADDR_WIDTH(a_hi_size+a_lo_size))
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dpram (
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dpram (
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.d_a(wdata),
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.d_a(wdata),
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.adr_a({onehot2bin(write),wadr}),
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.adr_a({onehot2bin(write_enable),wadr}),
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.we_a(|(write)),
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.we_a(write),
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.clk_a(clk1),
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.clk_a(clk1),
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.q_b(q),
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.q_b(q),
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.adr_b({onehot2bin(read),radr}),
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.adr_b({onehot2bin(read_enable),radr}),
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.clk_b(clk2) );
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.clk_b(clk2) );
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endmodule
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endmodule
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