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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [sd_fifo.v] - Diff between revs 12 and 13

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Rev 12 Rev 13
Line 169... Line 169...
                      (wb_adr_i==2'd1) ? {wb_adr_i,radr2} :
                      (wb_adr_i==2'd1) ? {wb_adr_i,radr2} :
                      (wb_adr_i==2'd2) ? {wb_adr_i,wadr3} :
                      (wb_adr_i==2'd2) ? {wb_adr_i,wadr3} :
                      {wb_adr_i,radr4};
                      {wb_adr_i,radr4};
   assign dpram_a_b = (sd_adr_i==2'd0) ? {sd_adr_i,radr1} :
   assign dpram_a_b = (sd_adr_i==2'd0) ? {sd_adr_i,radr1} :
                      (sd_adr_i==2'd1) ? {sd_adr_i,wadr2} :
                      (sd_adr_i==2'd1) ? {sd_adr_i,wadr2} :
                      (sd_adr_i==2'd3) ? {sd_adr_i,radr3} :
                      (sd_adr_i==2'd2) ? {sd_adr_i,radr3} :
                      {sd_adr_i,wadr4};
                      {sd_adr_i,wadr4};
 
 
 
 
   vfifo_dual_port_ram_dc_dw
   vfifo_dual_port_ram_dc_dw
/*     #
/*     #

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