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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_async_cmp.v] - Diff between revs 6 and 7

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module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
 
 
 
   parameter ADDR_WIDTH = 4;
 
   parameter N = ADDR_WIDTH-1;
 
 
 
   parameter Q1 = 2'b00;
 
   parameter Q2 = 2'b01;
 
   parameter Q3 = 2'b11;
 
   parameter Q4 = 2'b10;
 
 
 
   parameter going_empty = 1'b0;
 
   parameter going_full  = 1'b1;
 
 
 
   input [N:0]  wptr, rptr;
 
   output reg   fifo_empty, fifo_full;
 
   input        wclk, rclk, rst;
 
 
 
   reg  direction, direction_set, direction_clr;
 
 
 
   wire async_empty, async_full;
 
   reg  fifo_full2, fifo_empty2;
 
 
 
   // direction_set
 
   always @ (wptr[N:N-1] or rptr[N:N-1])
 
     case ({wptr[N:N-1],rptr[N:N-1]})
 
       {Q1,Q2} : direction_set <= 1'b1;
 
       {Q2,Q3} : direction_set <= 1'b1;
 
       {Q3,Q4} : direction_set <= 1'b1;
 
       {Q4,Q1} : direction_set <= 1'b1;
 
       default : direction_set <= 1'b0;
 
     endcase
 
 
 
   // direction_clear
 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
 
     if (rst)
 
       direction_clr <= 1'b1;
 
     else
 
       case ({wptr[N:N-1],rptr[N:N-1]})
 
         {Q2,Q1} : direction_clr <= 1'b1;
 
         {Q3,Q2} : direction_clr <= 1'b1;
 
         {Q4,Q3} : direction_clr <= 1'b1;
 
         {Q1,Q4} : direction_clr <= 1'b1;
 
         default : direction_clr <= 1'b0;
 
       endcase
 
 
 
   always @ (posedge direction_set or posedge direction_clr)
 
     if (direction_clr)
 
       direction <= going_empty;
 
     else
 
       direction <= going_full;
 
 
 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
 
   assign async_full  = (wptr == rptr) && (direction==going_full);
 
 
 
   always @ (posedge wclk or posedge rst or posedge async_full)
 
     if (rst)
 
       {fifo_full, fifo_full2} <= 2'b00;
 
     else if (async_full)
 
       {fifo_full, fifo_full2} <= 2'b11;
 
     else
 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
 
 
 
   always @ (posedge rclk or posedge async_empty)
 
     if (async_empty)
 
       {fifo_empty, fifo_empty2} <= 2'b11;
 
     else
 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
 
 
 
endmodule // async_comp
 
 
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