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https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_async_cmp.v] - Diff between revs 25 and 28
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| Rev 25 |
Rev 28 |
| Line 56... |
Line 56... |
input [N:0] wptr, rptr;
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input [N:0] wptr, rptr;
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output reg fifo_empty;
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output reg fifo_empty;
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output fifo_full;
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output fifo_full;
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input wclk, rclk, rst;
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input wclk, rclk, rst;
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`ifndef GENERATE_DIRECTION_AS_LATCH
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wire direction;
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wire direction;
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`endif
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`ifdef GENERATE_DIRECTION_AS_LATCH
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reg direction;
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`endif
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reg direction_set, direction_clr;
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reg direction_set, direction_clr;
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wire async_empty, async_full;
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wire async_empty, async_full;
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wire fifo_full2;
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wire fifo_full2;
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reg fifo_empty2;
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reg fifo_empty2;
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