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https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram.v] - Diff between revs 16 and 18
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| Rev 16 |
Rev 18 |
| Line 23... |
Line 23... |
`else
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`else
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clk
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clk
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`endif
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`endif
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);
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);
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parameter DATA_WIDTH = `DATA_WIDTH;
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parameter DATA_WIDTH = 32;
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parameter ADDR_WIDTH = `ADDR_WIDTH;
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parameter ADDR_WIDTH = 8;
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input [(DATA_WIDTH-1):0] d_a;
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input [(DATA_WIDTH-1):0] d_a;
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input [(ADDR_WIDTH-1):0] adr_a;
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input [(ADDR_WIDTH-1):0] adr_a;
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input [(ADDR_WIDTH-1):0] adr_b;
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input [(ADDR_WIDTH-1):0] adr_b;
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input we_a;
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input we_a;
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