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https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram_dc_dw.v] - Diff between revs 4 and 7
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| Rev 4 |
Rev 7 |
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Line 10... |
d_b,
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d_b,
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we_b,
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we_b,
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clk_b
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clk_b
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);
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);
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parameter DATA_WIDTH = 8;
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parameter DATA_WIDTH = 8;
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parameter ADDR_WIDTH = 9;
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parameter ADDR_WIDTH = 11;
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input [(DATA_WIDTH-1):0] d_a;
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input [(DATA_WIDTH-1):0] d_a;
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input [(ADDR_WIDTH-1):0] adr_a;
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input [(ADDR_WIDTH-1):0] adr_a;
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input [(ADDR_WIDTH-1):0] adr_b;
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input [(ADDR_WIDTH-1):0] adr_b;
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input we_a;
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input we_a;
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output [(DATA_WIDTH-1):0] q_b;
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output [(DATA_WIDTH-1):0] q_b;
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