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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [include/] [versatile_io_defines.v] - Diff between revs 4 and 6

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Rev 4	Rev 6
Line 3...	Line 3...
`//=tab UART`	`//=tab UART`
`define UART0	`define UART0
`define UART0_BASE_ADR 32'h92000000	`define UART0_BASE_ADR 32'h92000000
`define UART0_MEM_MAP_HI 31	`define UART0_MEM_MAP_HI 31
`define UART0_MEM_MAP_LO 24	`define UART0_MEM_MAP_LO 24
	`ifdef UART0
	`define UART
	`endif
`//=comment`	`//=comment`
//`define UART1	//`define UART1
`define UART1_BASE 32'h92100000	`define UART1_BASE 32'h92100000
`define UART1_MEM_MAP_HI 31	`define UART1_MEM_MAP_HI 31
`define UART1_MEM_MAP_LO 24	`define UART1_MEM_MAP_LO 24
	`ifdef UART1
	`ifndef UART
	`define UART
	`endif
	`endif

`No newline at end of file`	`No newline at end of file`

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