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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [top/] [versatile_io_top.v] - Diff between revs 6 and 14

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Rev 6 Rev 14
Line 47... Line 47...
`ifdef UART0
`ifdef UART0
wire uart0_cs;
wire uart0_cs;
assign uart0_cs = wbs_adr_i[uart0_mem_map_hi:uart0_mem_map_lo] == uart0_base_adr[uart0_mem_map_hi:uart0_mem_map_lo];
assign uart0_cs = wbs_adr_i[uart0_mem_map_hi:uart0_mem_map_lo] == uart0_base_adr[uart0_mem_map_hi:uart0_mem_map_lo];
wire [7:0] uart0_temp;
wire [7:0] uart0_temp;
wire uart0_ack_o;
wire uart0_ack_o;
uart_top uart0  (
/*
    .wb_clk_i(wbs_clk), .wb_rst_i(wbs_rst),
uart_top uart0  (
    // Wishbone signals
    .wb_clk_i(wbs_clk), .wb_rst_i(wbs_rst),
    .wb_adr_i(wbs_adr_i[2:0]), .wb_dat_i(tobyte(wbs_sel_i,wbs_dat_i)), .wb_dat_o(uart0_temp), .wb_we_i(wbs_we_i), .wb_stb_i(wbs_stb_i), .wb_cyc_i(wbs_cyc_i & uart0_cs), .wb_ack_o(uart0_ack_o), .wb_sel_i(4'b0),
    // Wishbone signals
    .int_o(uart0_irq), // interrupt request
    .wb_adr_i(wbs_adr_i[2:0]), .wb_dat_i(tobyte(wbs_sel_i,wbs_dat_i)), .wb_dat_o(uart0_temp), .wb_we_i(wbs_we_i), .wb_stb_i(wbs_stb_i), .wb_cyc_i(wbs_cyc_i & uart0_cs), .wb_ack_o(uart0_ack_o), .wb_sel_i(4'b0),
 
    .int_o(uart0_irq), // interrupt request
 
    // UART     signals
 
    // serial input/output
 
    .stx_pad_o(uart0_tx_pad_o), .srx_pad_i(uart0_rx_pad_i),
 
    // modem signals
 
    .rts_pad_o(), .cts_pad_i(1'b0), .dtr_pad_o(), .dsr_pad_i(1'b0), .ri_pad_i(1'b0), .dcd_pad_i(1'b0) );
 
*/
 
uart16750_wb uart0(
    // UART     signals
    // UART     signals
    // serial input/output
    .rx(uart0_rx_pad_i),
    .stx_pad_o(uart0_tx_pad_i), .srx_pad_i(uart0_rx_pad_i),
    .tx(uart0_tx_pad_o),
    // modem signals
    .int(uart0_irq),
    .rts_pad_o(), .cts_pad_i(1'b0), .dtr_pad_o(), .dsr_pad_i(1'b0), .ri_pad_i(1'b0), .dcd_pad_i(1'b0) );
    // wishbone slave
 
    .wbs_dat_i(tobyte(wbs_sel_i,wbs_dat_i)),
 
    .wbs_adr_i(wbs_adr_i[2:0]),
 
    .wbs_we_i(wbs_we_i),
 
    .wbs_cyc_i(wbs_cyc_i & uart0_cs),
 
    .wbs_stb_i(wbs_stb_i),
 
    .wbs_dat_o(uart0_temp),
 
    .wbs_ack_o(uart0_ack_o),
 
    .wb_clk_i(wbs_clk),
 
    .wb_rst_i(wbs_rst) );
assign uart0_dat_o = mask( toword(uart0_temp), uart0_ack_o);
assign uart0_dat_o = mask( toword(uart0_temp), uart0_ack_o);
`else
`else
assign uart0_dat_o = 32'h0;
assign uart0_dat_o = 32'h0;
assign uart0_ack_o = 1'b0;
assign uart0_ack_o = 1'b0;
`endif
`endif

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