URL
https://opencores.org/ocsvn/versatile_io/versatile_io/trunk
Show entire file |
Details |
Blame |
View Log
Rev 3 |
Rev 5 |
Line 1... |
Line 1... |
SVN_PATH = http://opencores.org/ocsvn/uart16550/uart16550/trunk/rtl/verilog/
|
SVN_PATH = http://opencores.org/ocsvn/uart16550/uart16550/trunk/rtl/verilog/
|
|
|
DEFINE_FILES = uart_defines.v
|
#DEFINE_FILES = uart_defines.v
|
DEFINE_FILES += timescale.v
|
DEFINE_FILES = timescale.v
|
|
|
RTL_FILES = raminfr.v
|
RTL_FILES = raminfr.v
|
RTL_FILES += uart_debug_if.v
|
RTL_FILES += uart_debug_if.v
|
RTL_FILES += uart_receiver.v
|
RTL_FILES += uart_receiver.v
|
RTL_FILES += uart_regs.v
|
RTL_FILES += uart_regs.v
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.