URL https://opencores.org/ocsvn/versatile_io/versatile_io/trunk

Subversion Repositories versatile_io

[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [versatile_io.v] - Diff between revs 16 and 17

Rev 16	Rev 17
Line 1420...	Line 1420...
`endif	`endif
`input wbs_clk, wbs_rst,`	`input wbs_clk, wbs_rst,`
`input clk, rst`	`input clk, rst`
`);`	`);`

	`wire [31:0] uart0_dat_o;`
`ifdef UART0	`ifdef UART0
parameter uart0_mem_map_hi = `UART0_MEM_MAP_HI;	parameter uart0_mem_map_hi = `UART0_MEM_MAP_HI;
parameter uart0_mem_map_lo = `UART0_MEM_MAP_LO;	parameter uart0_mem_map_lo = `UART0_MEM_MAP_LO;
parameter [31:0] uart0_base_adr = `UART0_BASE_ADR;	parameter [31:0] uart0_base_adr = `UART0_BASE_ADR;
`endif	`endif