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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [versatile_io_module_inst.v] - Diff between revs 10 and 12

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Rev 10 Rev 12
Line 12... Line 12...
`ifdef B4
`ifdef B4
    .wbs_stall_o(wbs_vio_stall_o),
    .wbs_stall_o(wbs_vio_stall_o),
`endif
`endif
`ifdef UART0
`ifdef UART0
    .uart0_rx_pad_i(uart0_rx_pad_i),
    .uart0_rx_pad_i(uart0_rx_pad_i),
    .uart0_tx_pad_i(uart0_tx_pad_i),
    .uart0_tx_pad_o(uart0_tx_pad_o),
    .uart0_irq(vio_uart0_irq),
    .uart0_irq(vio_uart0_irq),
`endif
`endif
`ifdef UART1
`ifdef UART1
    .uart1_rx_pad_i(uart1_rx_pad_i),
    .uart1_rx_pad_i(uart1_rx_pad_i),
    .uart1_tx_pad_i(uart1_tx_pad_i),
    .uart1_tx_pad_o(uart1_tx_pad_o),
    .uart1_irq(vio_uart1_irq),
    .uart1_irq(vio_uart1_irq),
`endif
`endif
    .wbs_clk(wb_clk), .wbs_rst(wb_rst),
    .wbs_clk(wb_clk), .wbs_rst(wb_rst),
    .clk(clk33), .rst(rst33));
    .clk(clk33), .rst(rst33));
 
 
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