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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [versatile_io_wires.v] - Diff between revs 6 and 9

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`include "versatile_io_defines.v"
`include "versatile_io_defines.v"
wire [31:0] wbs_vio_dat_i;
 
wire [31:0] wbs_vio_adr_i;
 
wire  [3:0] wbs_vio_sel_i;
 
wire wbs_vio_we_i, wbs_vio_stb_i, wbs_vio_cyc_i;
 
wire [31:0] wbs_vio_dat_o;
 
wire wbs_vio_ack_o, wbs_vio_err_o;
 
`ifdef B4
`ifdef B4
wire wbs_vio_stall_o;
wire wbs_vio_stall_o;
`endif
`endif
`ifdef UART0
`ifdef UART0
wire vio_uart0_irq;
wire vio_uart0_irq;

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