URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 58 |
Rev 149 |
| Line 110... |
Line 110... |
input [4:0] s; // shift operand
|
input [4:0] s; // shift operand
|
input [1:0] opcode;
|
input [1:0] opcode;
|
output [31:0] dout;
|
output [31:0] dout;
|
|
|
parameter opcode_sll = 2'b00;
|
parameter opcode_sll = 2'b00;
|
//parameter opcode_srl = 2'b01;
|
parameter opcode_srl = 2'b01;
|
parameter opcode_sra = 2'b10;
|
parameter opcode_sra = 2'b10;
|
//parameter opcode_ror = 2'b11;
|
parameter opcode_ror = 2'b11;
|
|
|
|
parameter mult=0; // if set to 1 implemented based on multipliers which saves LUT
|
|
|
|
generate
|
|
if (mult==1) begin : impl_mult
|
wire sll, sra;
|
wire sll, sra;
|
assign sll = opcode == opcode_sll;
|
assign sll = opcode == opcode_sll;
|
assign sra = opcode == opcode_sra;
|
assign sra = opcode == opcode_sra;
|
|
|
wire [15:1] s1;
|
wire [15:1] s1;
|
| Line 183... |
Line 187... |
assign dout[7:0] = (s[4:3]==2'b00) ? tmp[0] :
|
assign dout[7:0] = (s[4:3]==2'b00) ? tmp[0] :
|
(sll) ? {8{1'b0}}:
|
(sll) ? {8{1'b0}}:
|
(s[4:3]==2'b01) ? tmp[1] :
|
(s[4:3]==2'b01) ? tmp[1] :
|
(s[4:3]==2'b10) ? tmp[2] :
|
(s[4:3]==2'b10) ? tmp[2] :
|
tmp[3];
|
tmp[3];
|
|
end else begin : impl_classic
|
|
reg [31:0] dout;
|
|
//E2_ifdef SYSTEMVERILOG
|
|
always_comb
|
|
//E2_else
|
|
always @ (din or s or opcode)
|
|
//E2_endif
|
|
case (opcode)
|
|
opcode_sll: dout = din << s;
|
|
opcode_srl: dout = din >> s;
|
|
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}}));
|
|
//opcode_ror: dout = not yet implemented
|
|
default: dout = din << s;
|
|
endcase
|
|
|
|
end
|
|
engenerate
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef LOGIC_UNIT
|
`ifdef LOGIC_UNIT
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.